Interrupt Mask Register (Imask) - Freescale Semiconductor MPC8313E Family Reference Manual

Powerquicc ii pro integrated processor

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Enhanced Three-Speed Ethernet Controllers

Internal data parity error. This bit indicates that the eTSEC has detected a parity error on its stored data,

which is likely to compromise the validity of recently transferred frames.

0 No parity errors detected.

1 Data held in the FIFO or filer arrays is expected to be corrupted due to a parity error.

Receive frame parse error for TCP/IP off-load. This bit indicates that a received frame could not be parsed

unambiguously, due to encapsulated header type fields contradicting each other.

0 Received frame parsed successfully.

1 Received frame parse revealed header inconsistencies.

Interrupt Mask Register (IMASK)

The interrupt mask register provides control over which possible interrupt events in the IEVENT register

are permitted to participate in generating hardware interrupts to the PIC. All implemented bits in this

IMASK registers are set, the PIC receives an interrupt (for each eTSEC these are grouped into transmit,

receive, and error/diagnostic interrupts). The interrupt signal remains asserted until either the IEVENT bit

is cleared, by writing a 1 to it, or by writing a 0 to the corresponding IMASK bit.

describes the IMASK register.

Offset eTSEC1:0x2_4014; eTSEC2:0x2_5014

MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3

Table 15-8. IEVENT Field Descriptions (continued)

Figure 15-5. IMASK Register Definition

Access: Read/Write

Freescale Semiconductor

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