Freescale Semiconductor MPC8313E Family Reference Manual page 762

Enhanced Three-Speed Ethernet Controllers
Table 15-11 describes the fields of the ECNTRL register.
Bits Name
0–16 — Reserved
17 CLRCNT Clear all statistics counters and carry registers.
0 Allow MIB counters to continue to increment and keep any overflow indicators.
1 Reset all MIB counters and CAR1 and CAR2.
This bit is self-resetting.
18 AUTOZ Automatically zero MIB counter values and carry registers.
0 The user must write the addressed counter zero after a host read.
1 The addressed counter value is automatically cleared to zero after a host read.
This is a steady state signal and must be set prior to enabling the Ethernet controller and must not be
changed without proper care.
19 STEN MIB counter statistics enabled.
0 Statistics not enabled
1 Enables internal counters to update
This is a steady state signal and must be set prior to enabling the Ethernet controller and must not be
changed without proper care.
20–24 — Reserved
25 GMIIM GMII interface mode. Not supported.
26 TBIM (Reduced) ten-bit interface mode. If this bit is set, reduced ten-bit interface (RTBI) mode is enabled. This
bit can be pin-configured at reset to set or clear. See
0 MII or RMII mode interface
1 RTBI mode interface
27 RPM Reduced-pin mode for Gigabit interfaces. If this bit is set, a reduced-pin interface is expected on
Ethernet interfaces. RPM and RMM are never set together. This register can be pin-configured at reset
to 0 or 1.
0 SGMII or MII in non-reduced-pin mode configuration
1 RGMII or RTBI reduced-pin mode
28 R100M RGMII/RMII 100 mode. This bit is ignored unless SGMIIM, RPM or RMM are set and MACCFG2[I/F
Mode] is assigned to 10/100 (01).
0 RGMII is in 10 Mbps mode
SGMII is in 10 Mbps mode, and every 100th SGMII Reference clock is used to transfer data
1 RGMII is in 100 Mbps mode
SGMII is in 100 Mbps mode, and every 10th SGMII Reference clock is used to transfer data
This bit must be cleared for 1-Gbps SGMII operation.
29 RMM Reduced-pin mode for 10/100 interfaces. If this bit is set, an RMII pin interface is expected. RMM must
be 0 if RPM = 1. This register can be pin-configured at reset to 0 or 1.
0 Non-RMII interface mode
1 RMII interface mode
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
15-32
Table 15-11. ECNTRL Field Descriptions
RMII is in 10 Mbps mode, and every 10th RMII Reference clock is used to transfer data
RMII is in 100 Mbps mode, and data is transferred on every Reference clock
Description
Section 4.3.2, "Reset Configuration Words."
Freescale Semiconductor