Carry Mask Register 2 (Cam) - Freescale Semiconductor MPC8313E Family Reference Manual

Bits
19
20
21
22
23
24
25
26
27
28
29
30
31
15.5.3.6.47 Carry Mask Register 2 (CAM2)
While one of the below mask bits are cleared, the corresponding carry bit in CAR2 is allowed to cause
interrupt indications in register IEVENT[MSR0]. These bits default to a set state.
the definition for the CAM2 register.
Offset eTSEC1:0x2_473C; eTSEC2:0x2_573C
0
R
W
Reset 0 0 0
16 17 18
R
M2 M2 M2
TUN TFG TBY
W
Reset 1 1 1
Figure 15-99. Carry Mask Register 2 (CAM2) Register Definition
Table 15-103 describes the fields of the CAM2 register.
Bits
0–11
12
13
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 15-102. CAM1 Field Descriptions (continued)
Name
M1RBC Mask register 1 RBCA counter carry bit mask
M1RXC Mask register 1 RXCF counter carry bit mask
M1RXP Mask register 1 RXPF counter carry bit mask
M1RXU Mask register 1 RXUO counter carry bit mask
M1RAL Mask register 1 RALN counter carry bit mask
M1RFL Mask register 1 RFLR counter carry bit mask
M1RCD Mask register 1 RCDE counter carry bit mask
M1RCS Mask register 1 RCSE counter carry bit mask
M1RUN Mask register 1 RUND counter carry bit mask
M1ROV Mask register 1 ROVR counter carry bit mask
M1RFR Mask register 1 RFRG counter carry bit mask
M1RJB Mask register 1 RJBR counter carry bit mask
M1RDR Mask register 1 RDRP counter carry bit mask
—
0 0 0 0
19 20 21 22
M2 M2 M2 M2
TPK TMC TBC TPF
1 1 1 1
Table 15-103. CAM2 Field Descriptions
Name
— Reserved
M2TJB Mask register 2 TJBR counter carry bit mask
M2TFC Mask register 2 TFCS counter carry bit mask
Enhanced Three-Speed Ethernet Controllers
Description
0 0 0 0
23 24 25 26
M2 M2 M2 M2
TDF TED TSC TMA
1 1 1 1
Description
Figure 15-99 describes
Access: Read/Write
11 12 13 14
M2 M2 M2
TJB TFC TCF
0 1 1 1
27 28 29 30
M2 M2 M2
—
TLC TXC TNC
1 1 1 0
15
M2
TOV
1
31
M2
TDP
1
15-105