Aesu End-Of-Message Register (Aesuemr) - Freescale Semiconductor MPC8313E Family Reference Manual

Security Engine (SEC) 2.2
Bits Name
53 CE Context error. An AESU key register, the key size register, data size register, mode register, or IV register was
modified while the AESU was processing.
0 Context error enabled
1 Context error disabled
54 KSE Key size error. An inappropriate value (non 16, 24 or 32 bytes) was written to the AESU key size register
(AESUKSR)
0 Key size error enabled
1 Key size error disabled
55 DSE Data size error. Indicates that the number of bits to process is out of range.
0 Data size error enabled
1 Data size error disabled
56 ME Mode error. Indicates that invalid data was written to a register or a reserved mode bit was set.
0 Mode error enabled
1 Mode error disabled
57 AE Address error. An illegal read or write address was detected within the AESU address space.
1 Address error disabled
0 Address error enabled
58 OFE Output FIFO error. The shared symmetric output FIFO was detected non-empty upon write of AESU data size
register (AESUDSR)
0 Output FIFO non-empty error enabled
1 Output FIFO non-empty error disabled
59 IFE Input FIFO error. The shared symmetric input FIFO was detected non-empty upon generation of done
interrupt
0 Input FIFO non-empty error enabled
1 Input FIFO non-empty error disabled
60 — Reserved
61 IFO Input FIFO overflow. The shared symmetric input FIFO has been pushed while full.
0 Input FIFO overflow error enabled
1 Input FIFO overflow error disabled
62 OFU Output FIFO underflow. The shared symmetric output FIFO has been read while empty.
0 Output FIFO underflow error enabled
1 Output FIFO underflow error disabled
63 — Reserved
14.4.3.8

AESU End-of-Message Register (AESUEMR)

The AESU end-of-message register (AESUEMR), shown in
operation may be completed. After the final message block is written to the shared symmetric input FIFO,
the AESUEMR must be written. The value in the data size register (AESUDSR) is used to determine how
many bits of the final message block (always 128) will be processed. Writing to the AESUEMR causes the
AESU to process the final block of a message, allowing it to signal DONE. A read of the AESUEMR will
always return a zero value.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
14-48
Table 14-30. AESUICR Field Descriptions (continued)
Description
Figure 14-33, is used to indicate an AES
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