Flash Command Register (Fcr) - Freescale Semiconductor MPC8313E Family Reference Manual

Powerquicc ii pro integrated processor
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Enhanced Local Bus Controller
Offset 0x0E4
0
3
4
R
OP0
W
Reset
Table 10-25
describes FIR fields.
Bits
Name
0–3
OP0
FCM operation codes. OP0 is executed first, followed by OP1, through to OP7.
0000 NOP—No-operation and end of operation sequence
4–7
OP1
0001 CA—Issue current column address as set in FPAR, with length set by ORx[PGS]
0010 PA—Issue current block+page address as set in FBAR and FPAR, with length set by FMR[AL]
8–11
OP2
0011 UA—Issue user-defined address byte from next AS field in MDR
12–15
OP3
0100 CM0—Issue command from FCR[CMD0]
0101 CM1—Issue command from FCR[CMD1]
16–19
OP4
0110 CM2—Issue command from FCR[CMD2]
0111 CM3—Issue command from FCR[CMD3]
20–23
OP5
1000 WB—Write FBCR bytes of data from current FCM buffer to Flash device
24–27
OP6
1001 WS—Write one byte (8b port) of data from next AS field of MDR to Flash device
1010 RB—Read FBCR bytes of data from Flash device into current FCM RAM buffer
28–31
OP7
1011 RS—Read one byte (8b port) of data from Flash device into next AS field of MDR
1100 CW0—Wait for LFRB to return high or time-out, then issue command from FCR[CMD0]
1101 CW1—Wait for LFRB to return high or time-out, then issue command from FCR[CMD1]
1110 RBW—Wait for LFRB to return high or time-out, then read FBCR bytes of data from Flash device into
current FCM RAM buffer
1111 RSW—Wait for LFRB to return high or time-out, then read one byte (8b port) of data from Flash device
into next AS field of MDR

10.3.1.19 Flash Command Register (FCR)

The local bus Flash command register (FCR), shown in
EEPROM command bytes that may be referenced by opcodes in FIR during FCM operation. The values
of the commands should follow the manufacturer's datasheet for the relevant NAND Flash device.
Offset 0x0E8
0
R
CMD0
W
Reset
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
10-36
7
8
11 12
OP1
OP2
Figure 10-22. Flash Instruction Register
Table 10-25. FIR Field Descriptions
7
8
CMD1
Figure 10-23. Flash Command Register
15 16
19 20
OP3
OP4
All zeros
Description
Figure
10-23, holds up to four NAND Flash
15 16
CMD2
All zeros
Access: Read/Write
23 24
27 28
OP5
OP6
Access: Read/Write
23 24
CMD3
Freescale Semiconductor
31
OP7
31

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