Sys_Clk_In Division - Freescale Semiconductor MPC8313E Family Reference Manual

Bits Name
14–15 Reserved
16–18 TSEC1M
19–21 TSEC2M
22–27 Reserved
28 TLE
29 LALE
30–31 Reserved
4.5.1.6, 4-36
4.5.2.1, 4-38
Address 0x0_0A00
0 1
R LBCM DDRCM SVCOD SPMF CKID
W
n n
Reset
1
See Table 4-34 for reset values.
Bits Name
0 LBCM Local bus memory controller clock mode.
1 DDRCM DDR SDRAM memory controller clock mode.
2–3 SVCOD System PLL VCO division
4–7 SPMF System PLLmultiplication factor
8 CKID SYS_CLK_IN division factor. Reflects the value of
CFG_CLKIN_DIV input signal during the reset flow.
9–15 COREPLL Core PLL configuration.
16–31 — Reserved
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Field Values when
CFG_RESET_SOURCE[0:3] = 1000–1100
1000 1001 1010
00
101 011 000
000 101 001
000000
0
0
00
Change the first sentence to the following: "RCR, shown in Figure 4-11, can be
used by software to initiate a hard reset sequence."
Update Figure 4-13, "System PLL Mode Register," to show as follows:
2 3 4 7 8 9
n n n n n n n n n n n n n n n n n n n n n n
Figure 4-13. System PLL Mode Register
In addition, update Table 4-34, "System PLL Mode Register Bit Settings," to say
as follows:
Table 4-34. System PLL Mode Register Bit Settings
Meaning
1011 1100
—
001 000 000 = MII mode
001 = RMII
101 011
011 = RGMII mode
101 = RTBI mode
—
Big-endian mode
Normal timing
—
15 16
COREPLL
Section 4.3.2.1, "Reset Configuration Word Low
Register (RCWLR)"
Section 4.3.2.1, "Reset Configuration Word Low
Register (RCWLR)"
Section 4.3.2.1.1, "System PLL VCO Division"
Section 4.3.2.1.2, "System PLL Configuration"
Section 4.3.1.2, "CLKINSYS_CLK_IN Division"
See the applicable device hardware
specification.
Revision History
Meaning
Access: Read only
—
n n n n n n n n
Description
—
31
1
A-3