Freescale Semiconductor MPC8313E Family Reference Manual page 463

Table 10-3. Enhanced Local Bus Controller Registers (continued)
Offset
0x0C4 LTECCR—Transfer error ECC register
0x0C8– Reserved
0x0CC
0x0D0 LBCR—Configuration register
0x0D4 LCRR—Clock ratio register
0x0D8–0x0DC Reserved
0x0E0 FMR—Flash mode register
0x0E4 FIR—Flash instruction register
0x0E8 FCR—Flash command register
0x0EC FBAR—Flash block address register
0x0F0 FPAR—Flash page address register
0x0F4 FBCR—Flash byte count register
0x0F8–0x0FC Reserved
0x100 FECC0—Flash ECC block 0 register
0x104 FECC1—Flash ECC block 1 register
0x108 FECC2—Flash ECC block 2 register
0x10C FECC3—Flash ECC block 3 register
10.3.1 Register Descriptions
This section provides a detailed description of the eLBC configuration, status, and control registers with
detailed bit and field descriptions.
Address offsets in the eLBC address range that are not defined in
reading or writing. Similarly, only zero should be written to reserved bits of defined registers, as writing
ones can have unpredictable results in some cases.
Bits designated as write-one-to-clear are cleared only by writing ones to them. Writing zeros to them has
no effect.
10.3.1.1 Base Registers (BR0–BR3)
The base registers (BRn), shown in
memory bank. The memory controller uses this information to compare the address bus value with the
current address accessed. Each register (bank) includes a memory attribute and selects the machine for
memory operation handling. Note that after system reset, BR0[V] is set, BR1[V]–BR3[V] are cleared, and
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Enhanced Local Bus Controller
Register
Figure 10-2, contain the base address and address types for each
—Block Base Address 0x0_5000
Access
w1c
—
R/W
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
—
R
R
R
R
Table 10-3
Enhanced Local Bus Controller
Reset Section/Page
All zeros 10.3.1.14/10-31
— —
0x0004_0000 10.3.1.15/10-31
0x8000_0008 10.3.1.16/10-33
— —
0x0000_0 n 00 10.3.1.17/10-34
All zeros 10.3.1.18/10-35
All zeros 10.3.1.19/10-36
All zeros 10.3.1.20/10-37
All zeros 10.3.1.21/10-37
All zeros 10.3.1.22/10-39
— —
All zeros 10.3.1.23/10-39
All zeros 10.3.1.23/10-39
All zeros 10.3.1.23/10-39
All zeros 10.3.1.23/10-39
should not be accessed for
10-9