Receive Control Frame Packet Counter (Rxcf); Receive Pause Frame Packet Counter (Rxpf) - Freescale Semiconductor MPC8313E Family Reference Manual

Enhanced Three-Speed Ethernet Controllers

15.5.3.6.13 Receive Control Frame Packet Counter (RXCF)

Figure 15-65 describes the definition for the RXCF register.
Offset eTSEC1:0x2_46B0; eTSEC2:0x2_56B0
0
R
W
Reset
Figure 15-65. Receive Control Frame Packet Counter Register Definition
Table 15-69 describes the fields of the RXCF register.
Bits Name
0–15 — Reserved
16–31 RXCF Receive control frame packet counter. Increments for each MAC control frame received (PAUSE and
unsupported) with valid CRC and of lengths 64 to 1518 (non VLAN) or 1522 (VLAN).

15.5.3.6.14 Receive Pause Frame Packet Counter (RXPF)

Figure 15-66 describes the definition for the RXPF register.
Offset eTSEC1:0x2_46B4; eTSEC2:0x2_56B4
0
R
W
Reset
Figure 15-66. Receive Pause Frame Packet Counter Register Definition
Table 15-70 describes the fields of the RXPF register.
Bits Name
0–15 — Reserved
16–31 RXPF Receive PAUSE frame packet counter. Increments each time a PAUSE MAC control frame is
received with valid CRC and of lengths 64 to 1518 (non VLAN) or 1522 (VLAN).
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
15-86
—
All zeros
Table 15-69. RXCF Field Descriptions
—
All zeros
Table 15-70. RXPF Field Descriptions
15 16
Description
15 16
Description
Access: Read/Write
RXCF
Access: Read/Write
RXPF
Freescale Semiconductor
31
31