Freescale Semiconductor MPC8313E Family Reference Manual page 714

Powerquicc ii pro integrated processor
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Security Engine (SEC) 2.2
Table 14-34
shows the values of channel states.
Value
0x00
IDLE
0x01
PROCESS_HEADER
0x02
FETCH_DESCRIPTOR
0x03
CHANNEL_DONE
0x04
CHANNEL_DONE_IRQ
0x05
CHANNEL_DONE_WRITEBACK
0x06
CHANNEL_DONE_NOTIFICATION
0x07
CHANNEL_ERROR
0x08
REQUEST_PRI_CHA
0x09
INC_DATA_PAIR_POINTER
0x0A
DELAY_DATA_PAIR_UPDATE
0x0B
EVALUATE_DATA_PAIRS
0x0C
WRITE_RESET_PRI
0x0D
RELEASE_PRI_CHA
0x0E
WRITE_RESET_SEC
0x0F
RELEASE_SEC_CHA
0x10
PROCESS_DATA_PAIRS
0x11
WRITE_MODE_PRI
0x12
WRITE_MODE_SEC
0x13
WRITE_DATASIZE_PRI
0x14
DELAY_RNGA_DONE
0x15
WRITE_DATASIZE_SEC_SNOOPIN
0x16
TRANS_REQUEST_WRITE_SNOOPIN
0x17
DELAY_PRI_SEC_DONE
0x18
TRANS_REQUEST_WRITE
0x19
WRITE_KEY_SIZE
0x1B
DELAY_PRI_DONE
0x1E
WRITE_DATASIZE_SEC_SNOOPOUT
0x1F
TRANS_REQUEST_READ_SNOOPOUT
0x20
DELAY_SEC_DONE
0x21
TRANS_REQUEST_READ
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
14-60
Table 14-34. CHN_STATE Field Values
Channel State
Value
Channel State
0x22
EVALUATE_RESET
0x23
RESET_WRITE_RESET_PRI
0x24
RESET_RELEASE_PRI_CHA
0x25
RESET_WRITE_RESET_SEC
0x26
RESET_RELEASE_SEC_CHA
0x27
RESET_CHANNEL
0x28
WRITE_DATASIZE_PRI_POST
0x29
RESET_RELEASE_ALL
0x2A
RESET_RELEASE_ALL_DELAY
0x2B
REQUEST_SEC_CHA
0x2C
WRITE_DATASIZE_SEC
0x2D
WRITE_ICV_SIZE
0x2E
WRITE_SEC_CHA_GO_SNOOPOUT
0x2F
WRITE_PRI_CHA_GO_SNOOPIN
0x30
WRITE_SEC_CHA_GO_SNOOPIN
0x31
DELAY_1CYCLE
0x33
TRANS_EXTENT_READ
0x34
TRANS_EXTENT3
0x35
TRANS_EXTENT4
0x36
XOR_WRITE_READ_REG
0x37
DELAY_SEC_DONE_TLS
0x38
MAC_TO_CIPHER
0x39
MAC_TO_CIPHER_DONE
0x3A
READ_PRI_STATUS
0x3C
READ_SEC_STATUS
Others
Reserved
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