Inbound Message Registers (Imr0–Imr); Outbound Message Registers (Omr0–Omr) - Freescale Semiconductor MPC8313E Family Reference Manual

Bits Name
1 OM1IM Outbound message 1 interrupt mask.
0 Outbound message 1 interrupt is allowed
1 Outbound message 1 interrupt is masked
0 OM0IM Outbound message 0 interrupt mask.
0 Outbound message 0 interrupt is allowed
1 Outbound message 0 interrupt is masked
12.3.3 Inbound Message Registers (IMR0–IMR1)
The inbound message registers can be read from the PCI bus and the CSB in both host and agent modes.
They can be written only from the PCI bus.
Offset 0x050, 0x054
31
R
W
Reset
Table 12-4 describes the IMRn register.
Bits Name
31–0 IMSG n Inbound message n. Contains generic data to be passed between the local processor and external hosts.
12.3.4 Outbound Message Registers (OMR0–OMR1)
The outbound message registers can be read from the PCI bus and the CSB in both host and agent modes.
They can be written only from the CSB.
Offset 0x058, 0x05C
31
R
W
Reset
Table 12-5 describes the OMRn registers.
Bits Name
31–0 OMSG n Outbound message n . Contains generic data to be passed between the local processor and external hosts.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 12-3. OMIMR Field Descriptions (continued)
Figure 12-4
Figure 12-4. Inbound Message Registers (IMR0, IMR1)
Table 12-4. IMR0 and IMR1 Field Descriptions
Figure 12-5. Outbound Message Registers (OMR0–OMR1)
Table 12-5. OMR0 and OMR1 Field Descriptions
Description
shows the IMR0 and IMR1 fields.
IMSG n
All zeros
Description
OMSG n
All zeros
Description
DMA/Messaging Unit
Access: Read/Write
0
Access: Read/Write
0
12-5