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17.4.4.1
Clock Synchronization
Due to the wire AND logic on the SCLn line, a high-to-low transition on the SCLn line affects all devices
connected on the bus. The devices begin counting their low period when the master negates the SCLn line.
After a device has negated SCLn, it holds the SCLn line low until the clock high state is reached. However,
the change of low-to-high in a device clock may not change the state of SCLn if another device is still
within its low period. Therefore, SCLn is held low by the device with the longest low period. Devices with
shorter low periods enter a high wait state during this time. When all devices concerned have counted off
their low periods, SCLn is released and asserted. Then there is no difference between the devices' clocks
and the state of SCLn, and all the devices begin counting their high periods. The first device to complete
its high period negates SCLn again.
17.4.4.2
Input Synchronization and Digital Filter
The following sections describes synchronization of the input signals and the filtering of SCLn and SDAn
in detail.
17.4.4.2.1
Input Signal Synchronization
The input synchronization block synchronizes the input SCLn and SDAn signals to the system clock and
detects transitions of these signals.
Filtering of SCL n and SDA n Lines
17.4.4.2.2
The SCLn and SDAn inputs are filtered to eliminate noise. Three consecutive samples of the SCLn and
SDAn lines are compared to a pre-determined sampling rate. If they are all high, the output of the filter is
high. If they are all low, the output is low. If they are any combination of highs and lows, the output is
whatever the value of the line was in the previous clock cycle.
The sampling rate is equal to a binary value stored in the frequency register I2CDFSRR. The duration of
the sampling cycle is controlled by a down counter. This allows a software write to the I2CDFSRR to
control the filtered sampling rate.
17.4.4.3
Clock Stretching
Slaves can use the clock synchronization mechanism to slow down the transfer bit rate. After the master
has driven SCLn low, the slave can drive SCLn low for the required period and then release it. If the slave
SCLn low period is greater than the master SCLn low period, the resulting SCLn low period is extended.
17.4.5
Boot Sequencer Mode
Boot sequencer mode is selected at power-on reset by the BOOTSEQ field of the high-order reset
configuration word. If boot sequencer mode is selected, the I
EEPROMs through the I
configuration registers. Note that as described in
default value for BOOTSEQ is 0b00, which corresponds to the I
power-up.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
2
C interface. EEPROMs can be programmed to initialize one or more
2
C module communicates with one or more
Section 4.3.2.2.3, "Boot Sequencer Configuration,"
2
C boot sequencer being disabled at
2
I
C Interfaces
the
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