Freescale Semiconductor MPC8313E Family Reference Manual page 454

DDR Memory Controller
enabled) before MEM_EN can be set, so a delay loop in the initialization code may be necessary if
software is enabling the memory controller. If DDR_SDRAM_CFG[BI] is not set, the DDR memory
controller conducts an automatic initialization sequence to the memory, which follows the memory
specifications. If the bypass initialization mode is used, then software can initialize the memory through
the DDR_SDRAM_MD_CNTL register.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
9-56 Freescale Semiconductor