Pci Arbiter Control Register (Pciacr) - Freescale Semiconductor MPC8313E Family Reference Manual

Table 13-40. PCI Function Configuration Register Field Descriptions (continued)
Bits Name
2 TLTD
1 MLTD
0 HA

13.3.3.25 PCI Arbiter Control Register (PCIACR)

Figure 13-43 shows the PCI arbiter control register (PCIACR) fields.
Offset 0x46
15 14 13
R
AD PM —
W
Reset cfg 0 0
Table 13-41 shows the bit settings of the PCIACR.
Table 13-41. PCI Arbiter Control Register (PCIACR) Field Descriptions
Bits Name
15 AD
14 PM
13 —
12 PBMD
11–7 —
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Target latency timeout disable. Determines whether the PCI controller, while acting as a PCI target,
times out when the first data phase of a transaction has not completed in 16 PCI cycles.
0 Target latency timeout enabled.
1 Target latency timeout disabled.
Master latency timer disable. Determines whether the PCI controller, while acting as a PCI master,
terminates a transaction upon the expiration of the master latency timer.
0 Master latency timer enabled.
1 Master latency timer disabled.
Host/Agent. Indicates whether the PCI controller is in host mode or agent mode. It provides the
value of the PCI_HOST—PCI host configuration bit is sampled at the end of the reset sequence.
0 Host mode
1 Agent mode
12 11
PMBD —
0 0 0 0
Figure 13-43. PCI Arbiter Control Register (PCIACR)
Arbiter disable. Indicates whether the PCI controller functions as the arbiter for the PCI bus. It
provides the value of the PCI arbiter enable configuration bit as sampled at the end of the reset
sequence. SeeChapter 4, "Reset, Clocking, and Initialization,"
configuration.
0 Arbiter enabled
1 Arbiter disabled
Parking mode. Controls which device receives a bus grant when there are no outstanding bus
requests and the bus is idle.
0 The bus is parked with the last device to use the bus.
1 The bus is parked with the PCI controller.
Reserved
PCI broken master disable. Determines whether the PCI controller ignores the bus requests of an
initiator that requests the bus for an excessive period without using it.
0 An initiator that requests the bus and receives the grant must begin using the bus within 16 PCI
clock periods after the bus becomes idle or its request is subsequently ignored.
1 No requests are ignored.
Reserved
Description
7 6 5
PRI0 PRI1
0 0 0 0
Description
PCI Bus Interface
Access: Read/Write
4 3 1
PRI2 —
0 0 0 0
for more information on reset
0
MPRI
0
13-39