Freescale Semiconductor MPC8313E Family Reference Manual page 39

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Figure
Number
1-1 MPC8313E Block Diagram .................................................................................................... 1-2
1-2 MPC8313E Integrated e300c3 Core Block Diagram.............................................................. 1-9
1-3 Integrated Security Engine Functional Blocks...................................................................... 1-10
1-4 USB Controllers Port Configuration..................................................................................... 1-13
1-5 MPC8313E Serving as the Main CPU in a Low-End Printer Application ........................... 1-19
1-6 MPC8313E I/O Processor Implementation in a High-End Printer Application ................... 1-20
1-7 IEEE Std. 1588 in Test and Measurement ............................................................................ 1-21
1-8 IEEE Std. 1588 in Industrial Control .................................................................................... 1-22
1-9 MPC8313E as a WLAN Access Point .................................................................................. 1-23
1-10 MPC8313E as a Media Server .............................................................................................. 1-24
3-1 MPC8313E Signal Groupings (1 of 2).................................................................................... 3-3
3-2 MPC8313E Signal Groupings (2 of 2).................................................................................... 3-4
4-1 Power-On Reset Flow ............................................................................................................. 4-8
4-2 Hard Reset Flow...................................................................................................................... 4-9
4-3 Reset Configuration Word Low Register (RCWLR) ............................................................ 4-13
4-4 Reset Configuration Word High Register (RCWHR) ........................................................... 4-15
4-5 EEPROM Data Format for Reset Configuration Words Preload Command ........................ 4-24
4-6 EEPROM Contents ............................................................................................................... 4-25
4-7 Clock Subsystem Block Diagram ......................................................................................... 4-29
4-8 Reset Status Register (RSR).................................................................................................. 4-33
4-9 Reset Mode Register (RMR)................................................................................................. 4-34
4-10 Reset Protection Register (RPR)........................................................................................... 4-35
4-11 Reset Control Register (RCR)............................................................................................... 4-35
4-12 Reset Control Enable Register (RCER) ................................................................................ 4-36
4-13 System PLL Mode Register .................................................................................................. 4-37
4-14 Output Clock Control Register (OCCR) ............................................................................... 4-38
4-15 System Clock Control Register (SCCR) ............................................................................... 4-39
5-1 Local Memory Map Example ................................................................................................. 5-2
5-2 Internal Memory Map Registers' Base Address Register (IMMRBAR)................................ 5-6
5-3 Alternate Configuration Base Address Register (ALTCBAR) ............................................... 5-7
5-4 LBC Local Access Window n Base Address Registers (LBLAWBAR0–LBLAWBAR3) .... 5-8
5-5 LBC Local Access Window n Attributes Registers (LBLAWAR0–LBLAWAR3) ................ 5-9
5-6 PCI Local Access Window n Base Address Registers (PCILAWBAR0–PCILAWBAR1) . 5-10
5-7 PCI Local Access Window n Attributes Registers (PCILAWAR0–PCILAWAR1).............. 5-11
5-8 DDR Local Access Window n Base Address Registers (DDRLAWBAR0–DDRLAWBAR1)...
5-12
5-9 DDR Local Access Window n Attributes Registers (DDRLAWAR0–DDRLAWAR1) ....... 5-13
5-10 System General Purpose Register Low (SGPRL)................................................................. 5-17
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
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