Mac Registers; Mac Configuration 1 Register (Maccfg) - Freescale Semiconductor MPC8313E Family Reference Manual

15.5.3.5

MAC Registers

This section describes the MAC registers.
15.5.3.5.1 MAC Configuration 1 Register (MACCFG1)
MACCFG1 is written by the user.
Offset eTSEC1:0x2_4500; eTSEC2:0x2_5500
0 1
R
Soft_Reset
W
Reset
16
R
—
W
Reset
Table 15-41 describes the fields of the MACCFG1 register.
\
Bits Name
0 Soft_Reset Soft reset. This bit is cleared by default. See
Procedure,"
0 Normal operation.
1 Place the entire MAC in reset except for the host interface.
1–11 — Reserved
12 Reset Rx MC Reset receive MAC control block. This bit is cleared by default.
0 Normal operation.
1 Place the receive part of the MAC in reset. This block detects control frames and contains the pause
13 Reset Tx MC Reset transmit MAC control block. This bit is cleared by default.
0 Normal operation.
1 Place the transmit part of the MAC in reset. This block multiplexes data and control frame transfers.
14 Reset Rx Fun Reset receive function block. This bit is cleared by default.
0 Normal operation.
1 Place the receive function in reset. This block performs the receive frame protocol.
15 Reset Tx Fun Reset transmit function block. This bit is cleared by default.
0 Normal operation.
1 Place the transmit function in reset. This block performs the frame transmission protocol.
16–22 — Reserved
23 Loop Back Loop back. This bit is cleared by default.
0 Normal operation.
1 Loop back the MAC transmit outputs to the MAC receive inputs.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Figure 15-37
—
22 23 24 25 26
Loop Back — Rx_Flow Tx_Flow
Figure 15-37. MACCFG1 Register Definition
Table 15-41. MACCFG1 Field Descriptions
for more information on setting this bit.
timers.
It also responds to XOFF PAUSE control frames.
Enhanced Three-Speed Ethernet Controllers
describes the definition for the MACCFG1 register.
11 12
Reset Rx MC Reset Tx MC Reset Rx Fun Reset Tx Fun
All zeros
27 28
Sync'd Rx EN
All zeros
Description
Section 15.6.2.2, "Soft Reset and Reconfiguring
Access: Mixed
13 14
29 30
Sync'd Tx EN
Rx_EN
15
31
Tx_EN
15-67