System External Interrupt Pending Register (Sepnr); System Mixed Interrupt Group A Priority Register (Smprr_A) - Freescale Semiconductor MPC8313E Family Reference Manual

Integrated Programmable Interrupt Controller (IPIC)
8.5.8

System External Interrupt Pending Register (SEPNR)

Each bit in the SEPNR, shown in
interrupt is received, the interrupt controller sets the corresponding SEPNR bit.
Offset 0x2C
0 1 2
R
1
IRQ0 IRQ1 IRQ2 IRQ3 IRQ4
W
Reset The reset values of implemented bits reflect the values of the external IRQ signals. Reserved bits are zeros.
16
R
W
Reset
1
This bit is valid only if the IRQ0 signal is configured as an external maskable interrupt (SEMSR[SIRQ0] = 0)
2
The user should drive all IRQ inputs to an inactive state prior to reset negation
Figure 8-11. System External Interrupt Pending Register (SEPNR)
Table 8-16 defines the bit fields of SEPNR.
Bits Name
IRQ n Each bit corresponds to an external interrupt source. When an external interrupt is received, the interrupt
0–4
controller sets the corresponding SEPNR bit.
When a pending interrupt is handled, the user must clear the corresponding SEPNR bit. For level triggered cases,
the software needs to cause the IRQn to negate which automatically clears the bit in SEPNR. For edge-triggered
cases, the software needs to clear the corresponding bit in SEPNR.
SEPNR bits are cleared by writing ones to them. Because the user can only clear bits in this register, writing zeros
to this register has no effect.
Note that the SEPNR bit positions are not changed according to their relative priority.
5–31 — Write ignored, read = 0
8.5.9

System Mixed Interrupt Group A Priority Register (SMPRR_A)

The SMPRR_A, shown in
Offset 0x30
0 2 3
R
MIXA0P MIXA1P
W
Reset 0 0 0 0 0
Figure 8-12. System Mixed Interrupt Group A Priority Register (SMPRR_A)
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
8-18
Figure 8-11, corresponds to an external interrupt source. When an
3 4 5
Table 8-16. SEPNR Field Descriptions
Figure 8-12, defines the priority among the sources listed in
5 6 8 9 11 12
MIXA2P MIXA3P
1 0 1 0 0 1 1 0
—
All zeros
Description
15 16 18 19
— MIXA4P MIXA5P
0 0 0 1 0 0 1 0
Access: Read/write
—
Table
Access: Read/write
21 22 24 25 27 28
MIXA6P MIXA7P
1 1 1 0 1 1 1
Freescale Semiconductor
15
2
31
8-17.
31
—
0 0 0 0