Clock Source Modes; Gtm External Signal Description - Freescale Semiconductor MPC8313E Family Reference Manual

Powerquicc ii pro integrated processor
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System Configuration
Super-cascaded mode: In this mode, all four 16-bit timers can be internally cascaded to form a
64-bit counter. When working in the super-cascaded mode, the cascaded GTRFR, GTCPR, and
GTCNR should be referenced with two 32-bit bus cycles.
5.7.3.2

Clock Source Modes

The clock input to the timer's prescaler can be selected from three sources:
The system clock
The system slow go clock (system bus clock internally divided by 16)
The corresponding TINx pin
5.7.3.3
Reference Modes
Each timer can be configured to count until a reference is reached and then either begin a new time count
immediately or continue to run. The FRR bit of the corresponding GTMRR selects each mode.
Free run reference mode. The corresponding timer count continues to increment after the reference
value is reached.
Reset reference mode. The corresponding timer count is reset immediately after the reference value
is reached.
5.7.3.4
Capture Modes
Each timer has a 16-bit field in GTCPR, used to latch the value of the counter when a defined transition of
TINx is sensed by the corresponding input capture edge detector.
Normal gate mode enables the count on a falling edge of the TGATE pin and disables the count on
the rising edge of TGATE. This mode allows the timer to count conditionally, based on the state of
TGATE.
The restart gate mode performs the same function as normal mode, except it also resets the counter
on the falling edge of the TGATE pin. This mode has applications in pulse interval measurement
and bus monitoring.
5.7.4

GTM External Signal Description

This section provides an overview and detailed descriptions of the GTM signals.
There are four distinct external input timer capture signals (TIN1, TIN2, TIN3, and TIN4), four distinct
external input timer gate signals (TGATE1, TGATE2, TGATE3, and TGATE4), and four distinct external
timer output signals (TOUT1, TOUT2, TOUT3, and TOUT4). The GTM interface signals are defined in
Table
5-53.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
5-52
Freescale Semiconductor

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