Transmit Descriptor Base Address Registers (Tbase0–Tbase) - Freescale Semiconductor MPC8313E Family Reference Manual

TRANSMIT command is issued and the frame completes its transmission) in order to change the next
TxBD eTSEC transmits.
Offset eTSEC1:0x2_4184+8× n ; eTSEC2:0x2_5184+8× n
0
R
W
Reset
Table 15-24 describes the fields of the TBPTRn register.
Bits Name
0–28 TBPTR n Current TxBD pointer for TxBD ring n . Points to the current BD being processed or to the next BD the
transmitter uses when it is idling. When the end of the TxBD ring is reached, eTSEC initializes TBPTR n to
the value in the corresponding TBASE n . The TBPTR register is internally written by the eTSEC's DMA
controller during transmission. The pointer increments by eight (bytes) each time a descriptor is closed
successfully by the eTSEC. Note that the three least significant bits of this register are read-only and zero.
After an error condition, the eTSEC returns TBPTR n to point to the first BD of the frame partially transmitted.
29–31 — Reserved
15.5.3.2.10 Transmit Descriptor Base Address Registers (TBASE0–TBASE7)
The TBASEn registers are written by the user with the base address of each TxBD ring n. Each such value
must be divisible by eight, since the three least significant bits always write as 000.
the definition for the TBASEn registers.
Offset eTSEC1:0x2_4204+8× n ; eTSEC2:0x2_5204+8× n
0
R
W
Reset
Table 15-25 describes the fields of the TBASEn registers.
Bits Name
0–28 TBASE n Transmit base for ring n . TBASE defines the starting location in the memory map for the eTSEC TxBDs. This
field must be 8-byte aligned. Together with setting the W (wrap) bit in the last BD, the user can select how
many BDs to allocate for the transmit packets. The user must initialize TBASE before enabling the eTSEC
transmit function on the associated ring.
29–31 — Reserved
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
TBPTR n
Figure 15-19. TBPTR0–TBPTR7 Register Definition
Table 15-24. TBPTR n Field Descriptions
TBASE n
Figure 15-20. TBASE Register Definition
Table 15-25. TBASE0–TBASE7 Field Descriptions
Enhanced Three-Speed Ethernet Controllers
All zeros
Description
All zeros
Description
Access: Read/Write
28 29 31
—
Figure 15-20 describes
Access: Read/Write
28 29 31
—
15-47