Memory Accesses - Freescale Semiconductor MPC8313E Family Reference Manual

Address Arbitration
Address Termination
The core interface supports bus pipelining, allowing the address tenure of one transaction to overlap the
data tenure of another. The extent of the pipelining depends on external arbitration and control circuitry.
Similarly, the core supports split-bus transactions for systems with multiple potential bus masters—one
device can have mastership of the address bus while another has mastership of the data bus. Allowing
multiple bus transactions to occur simultaneously increases the available bus bandwidth for other activity
and, as a result, improves performance.
The core clocking structure allows the bus to operate at integer multiples of the core cycle time.
The following sections describe the core bus support for memory operations. Note that some signals
perform different functions depending on the addressing protocol used.
7.3.7.1

Memory Accesses

The e300 core CSB is a 64-bit data bus.
With a 64-bit CSB, memory accesses allow transfer sizes of 8, 16, 24, 32, 40, 48, 56, or 64 bits in one bus
clock cycle. Data transfers occur in either single-beat transactions or four-beat burst transactions.
Single-beat transactions are caused by noncached accesses that access memory directly (that is, reads and
writes when caching is disabled, caching-inhibited accesses, and stores in write-through mode). Four-beat
burst transactions, which always transfer an entire cache block (32 bytes), are initiated when a line is read
from or written to memory.
7.3.7.2 Signals
The e300 core signals are grouped as follows:
• Interrupts/Resets—These signals include the external interrupt signal (
cint
( ), checkstop signals, performance monitor signal (pm_event_in) via the PM counters, and both
soft reset and hard reset signals. They are used to interrupt and, under various conditions, to reset
the core.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Address Start
Address Transfer
Transfer Attribute
Clocks
Output Enable
Input Enable
Debug Control
Figure 7-5. Core Interface
Data Arbitration
Data Transfer
Data Termination
Interrupt, Checkstops
e300 Core
Reset
Processor Status
Debug Control
JTAG/Debug Interface
Test Interface
1.5 V
e300 Processor Core Overview
int
), critical interrupt signal
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