Deu Interrupt Status Register (Deuisr) - Freescale Semiconductor MPC8313E Family Reference Manual

Security Engine (SEC) 2.2
14.4.1.6

DEU Interrupt Status Register (DEUISR)

The DEU interrupt status register (DEUISR), shown in
bit in the DEUISR can only be set if the corresponding bit of the DEU interrupt control register (DEUICR)
is zero (see Section 14.4.1.7, "DEU Interrupt Control Register
If the DEUISR is non-zero, the DEU halts and the DEU error interrupt signal is asserted to the controller
(see Section 14.6.4.3, "Interrupt Status Register
channel-controlled access, an interrupt signal is generated to the channel to which this EU is assigned. The
EU error then appears in bit 55 of the channel pointer status register (see
channel error interrupt to the controller.
0
Field —
Reset
R/W
Addr
Table 14-15 describes DEUISR fields.
Bits Name
0–49 — Reserved
50 KPE Key parity error. Defined parity bits in the keys written to the key registers did not reflect odd parity correctly.
(Note that key register 2 and key register 3 are checked for parity only if the appropriate DEU mode register
bit indicates triple DES. Also, key register 3 is checked only if key size reg = 24. Key register 2 is checked
only if key size reg = 16 or 24.)
0 No error detected
1 Key parity error
51 IE Internal error. An internal processing error was detected while performing encryption.
0 No error detected
1 Internal error
Note: This bit will be asserted any time an enabled error condition occurs and can only be cleared by setting
52 ERE Early read error. The DEU IV register was read while the DEU was performing encryption.
0 No error detected
1 Early read error
53 CE Context error. A DEU key register, the key size register, data size register, mode register, or IV register was
modified while DEU was performing encryption.
0 No error detected
1 Context error
54 KSE Key size error. An inappropriate value (8 being appropriate for single DES, and 16 and 24 being appropriate
for triple DES) was written to the DEU key size register
0 No error detected
1 Key size error
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
14-24
49 50 51
KPE IE ERE CE KSE DSE ME
Figure 14-12. DEU Interrupt Status Register (DEUISR)
Table 14-15. DEUISR Field Descriptions
the corresponding bit in the interrupt control register or by resetting the DEU.
Figure 14-12, records occurrences of errors. Each
(DEUICR)").
(ISR)"). In addition, if the DEU is being operated through
52 53 54 55 56
0
R
DEU 0x3_2030
Description
Table 14-35) and generates a
57 58 59 60 61
AE OFE IFE IFU IFO OFU OFO
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62 63