Freescale Semiconductor MPC8313E Family Reference Manual page 783

Bits Name
29 RXF5 Receive frame event occurred on ring 5. Set by the eTSEC if IEVENT[RXF] was set in relation to receiving a
frame to this ring.
30 RXF6 Receive frame event occurred on ring 6. Set by the eTSEC if IEVENT[RXF] was set in relation to receiving a
frame to this ring.
31 RXF7 Receive frame event occurred on ring 7. Set by the eTSEC if IEVENT[RXF] was set in relation to receiving a
frame to this ring.
15.5.3.3.3 Receive Interrupt Coalescing Register (RXIC)
The RXIC register enables and configures the operational parameters for interrupt coalescing associated
with received frames. Figure 15-25
Offset eTSEC1:0x2_4310; eTSEC2:0x2_5310
0 1 2 3
R
ICEN ICCS —
W
Reset
Table 15-30 describes the fields of the RXIC register.
Bits Name
0 ICEN Interrupt coalescing enable
0 Interrupt coalescing is disabled. Interrupts are raised as they are received.
1 Interrupt coalescing is enabled. If the eTSEC receive frame interrupt is enabled (IMASK[RXFEN] is set),
an interrupt is raised when the threshold number of frames is reached (defined by RXIC[ICFT]) or when
the threshold timer expires (determined by RXIC[ICTT]).
1 ICCS Interrupt coalescing timer clock source.
0 The coalescing timer advances count every 64 eTSEC Rx interface clocks (TSECn_GTX_CLK).
1 The coalescing timer advances count every 64 system clocks. This mode is recommended for FIFO
operation.
2 — Reserved
3–10 ICFT Interrupt coalescing frame count threshold. While interrupt coalescing is enabled (RXIC[ICE] is set), this value
determines how many frames are received before raising an interrupt. The eTSEC threshold counter is reset
to ICFT following an interrupt. The value of ICFT must be greater than zero avoid unpredictable behavior.
11–15 — Reserved
16–31 ICTT Interrupt coalescing timer threshold. While interrupt coalescing is enabled (RXIC[ICE] is set), this value
determines the maximum amount of time after receiving a frame before raising an interrupt. If frames have
been received but the frame count threshold has not been met, an interrupt is raised when the threshold timer
reaches zero. The threshold timer is reset to the value in this field and begins counting down upon receiving
the first frame having its RxBD[I] bit set. The threshold value is represented in units equal to 64 periods of the
clock specified by RXIC[ICCS]. ICTT must be greater than zero to avoid unpredictable behavior.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 15-29. RSTAT Field Descriptions (continued)
describes the RXIC register.
10 11
ICFT
Figure 15-25. RXIC Register Definition
Table 15-30. RXIC Field Descriptions
Enhanced Three-Speed Ethernet Controllers
Description
15 16
—
All zeros
Description
Access: Read/Write
ICTT
15-53
31