Receive Oversize Packet Counter (Rovr); Receive Fragments Counter (Rfrg) - Freescale Semiconductor MPC8313E Family Reference Manual

Enhanced Three-Speed Ethernet Controllers

15.5.3.6.21 Receive Oversize Packet Counter (ROVR)

Figure 15-73 describes the definition for the ROVR register.
Offset eTSEC1:0x2_46D0; eTSEC2:0x2_56D0
0
R
W
Reset
Figure 15-73. Receive Oversize Packet Counter Register Definition
Table 15-77 describes the fields of the ROVR register.
Bits Name
0–15 — Reserved
16–31 ROVR Receive oversize packet counter. Increments each time a frame is received which exceeded 1518 (non
VLAN) or 1522 (VLAN) and contains a valid FCS and was otherwise well formed.

15.5.3.6.22 Receive Fragments Counter (RFRG)

Figure 15-74 describes the definition for the RFRG register.
Offset eTSEC1:0x2_46D4; eTSEC2:0x2_56D4
0
R
W
Reset
Table 15-78 describes the fields of the RFRG register.
Bits Name
0–15 — Reserved
16–31 RFRG Receive fragments counter. Increments for each frame received which is less than 64 bytes in length and
contains an invalid FCS. This includes integral and non-integral lengths.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
15-90
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Table 15-77. ROVR Field Descriptions
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Figure 15-74. Receive Fragments Counter Register Definition
Table 15-78. RFRG Field Descriptions
15 16
All zeros
Description
15 16
All zeros
Description
Access: Read/Write
ROVR
Access: Read/Write
RFRG
Freescale Semiconductor
31
31