Freescale Semiconductor MPC8313E Family Reference Manual page 343

Table 7-2 shows the bit definitions for HID0.
Bits Name
Enable mcp . The purpose of this bit is to mask out machine check interrupts caused by assertion of
0 EMCP
mcp , similar to how MSR[EE] can mask external interrupts.
0 Masks mcp . Asserting mcp does not generate a machine check interrupt or a checkstop.
1 Asserting mcp causes checkstop if MSR[ME] = 0 or a machine check interrupt if ME = 1
1 ECPE Enable cache parity errors.
0 Disables instruction and data cache parity error reporting
1 Allows a detected cache parity error to cause a machine check interrupt if MSR[ME] = 1 or a
Enable ap_in[0:3] and ape for address parity checking.
2 EBA
0 Disables address parity checking during a snoop operation
1 Allows an address parity error during snoop operations to cause a checkstop if MSR[ME] = 0 or a
Note: Do not set this bit; the CSB does not have parity signals.
3 EBD Enable dpe for data parity checking.
0 Disables data parity checking
1 Allows a data parity error during reads to cause a checkstop if MSR[ME] = 0 or a machine check
Note: Do not set this bit; the CSB does not have parity signals.
4 SBCLK clk_out output enable. Used in conjunction with HID0[ECLK] and hreset to configure clk_out. See
Table 7-3
5 — Reserved
6 ECLK clk_out output enable. Used in conjunction with HID0[SBCLK] and the hreset signal to configure
clk_out. See
7 PAR Disable precharge of artry_out
0 Precharge of artry_out enabled
1 Alters bus protocol slightly by preventing the processor from driving artry_out to high (negated) state.
8 DOZE Doze mode enable. Operates in conjunction with MSR[POW].
0 Doze mode disabled
1 Doze mode enabled. Doze mode is invoked by setting MSR[POW] while this bit is set. In doze mode,
9 NAP Nap mode enable. Operates in conjunction with MSR[POW].
0 Nap mode disabled
1 Nap mode enabled. Nap mode is invoked by setting MSR[POW] while this bit is set. In nap mode,
10 SLEEP Sleep mode enable. Operates in conjunction with MSR[POW].
0 Sleep mode disabled
1 Sleep mode enabled. Sleep mode is invoked by setting MSR[POW] while this bit is set. qreq is
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 7-2. e300 HID0 Bit Descriptions
checkstop if MSR[ME] = 0
machine check interrupt if MSR[ME] = 1
interrupt if MSR[ME] = 1
for settings.
Table 7-3 for settings.
If this is done, the integrated device must restore the signals to the high state.
the PLL, time base, and snooping remain active.
the PLL and time base remain active.
asserted to indicate that the processor is ready to enter sleep mode. If the system logic determines
that the processor may enter sleep mode, the quiesce acknowledge signal, qack, is asserted back
to the processor. Once qack assertion is detected, the processor enters sleep mode after several
processor clocks. At this point, the system logic may turn off the PLL by first configuring pll_cfg[0:6]
to PLL bypass mode, then disabling sysclk .
Function
e300 Processor Core Overview
7-21