Masking Interrupt Sources - Freescale Semiconductor MPC8313E Family Reference Manual

Integrated Programmable Interrupt Controller (IPIC)
8.6.7

Masking Interrupt Sources

By programming the system interrupt mask registers, SIMSRx and SEMSR, the user can mask interrupt
requests to the core. Each SIMSRx and SEMSR bit corresponds to an interrupt source. To enable an
interrupt, set the corresponding SIMSR or SEMSR bit. When a masked interrupt source has a pending
interrupt request, the corresponding SIPNRx or SEMSR bit is set, even though the interrupt is not
generated to the core. The user can mask all interrupt sources to implement a polling interrupt servicing
scheme.
When an interrupt source has multiple interrupting events, the user can individually mask these events by
programming a mask register within that particular block.
multiple interrupting events.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
8-34
Table 8-31. Interrupt Source Priority Levels (continued)
Priority
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
Interrupt Source Description
Reserved
Reserved
SYSD5 (Spread)
Reserved
Reserved
MIXB7 (Spread)
GTM1
Reserved
SYSA6 (Spread)
GTM5
Reserved
SYSD6 (Spread)
Reserved
Reserved
Reserved
Reserved
SYSA7 (Spread)
Reserved
Reserved
SYSD7 (Spread)
Reserved
Reserved
Table 8-31 shows which interrupt sources have
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