Freescale Semiconductor MPC8313E Family Reference Manual page 618

PCI Bus Interface
Address
00
02
04
06
08
09
0A
0B
0C
0D
0E
0F
10
14
18
1C
20
24
2C
2E
34
3C
3D
3E
3F
44
46
48
80
84
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
13-26
Table 13-22. PCI Configuration Space Registers
Vendor ID configuration register
Device ID configuration register
PCI command configuration register
PCI status configuration register
Revision ID configuration register
Standard programming interface
Subclass code configuration register
Base class code configuration register
Cache line size configuration register
Latency timer configuration register
Header type configuration register
BIST control configuration register
PIMMR base address register
GPL base address register 0
GPL base address register 1
GPL extended base address register 1
GPL base address register 2
GPL extended base address register 2
Subsystem vendor ID configuration register
Subsystem device ID configuration register
Capabilities pointer configuration register
Interrupt line configuration register
Interrupt pin configuration register
Minimum grant configuration register
Maximum latency configuration register
PCI function configuration register
PCI arbiter control register (PCIACR)
Hot swap register block
PCI power management register 0
PCI power management register 1
Use Access
R
R
R/W
Read/bit-reset
R
R
R
R
R/W
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R/W
R
R
R
R/W
R/W
R/W
R
R/W
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