Gigabit Ethernet Frame Reception - Freescale Semiconductor MPC8313E Family Reference Manual

Enhanced Three-Speed Ethernet Controllers
The transmitter also monitors for an abort condition and terminates the current frame if an abort condition
is encountered. In full-duplex mode the protocol is independent of network activity, and only the transmit
inter-frame gap must be enforced.
The transmitter implements full-duplex flow control. If a flow control frame is received, the MAC does
not service the transmitter's request to send data until the pause duration is over. If the MAC is currently
sending data after a pause frame has been received and processed, the MAC finishes sending the current
frame, then suspends subsequent frames (except a pause frame) until the pause duration is over. In
addition, the transmitter supports transmission of flow control frames through TCTRL[TFC_PAUSE]. The
transmit pause frame is generated internally based on the PAUSE register that defines the pause value to
be sent. Note that it is possible to send a pause frame while the pause timer has not expired.
The MAC automatically appends FCS (32-bit CRC) bytes to the frame if any of the following values are
set:
• TxBD[PAD/CRC] is set in first TxBD
• TxBD[TC] is set in first TxBD
• MACCFG2[PAD/CRC] is set
• MACCFG2[CRC] is set
The Tx_EN is negated after the FCS is sent. This notifies the PHY of the need to generate the illegal
Manchester encoding that signifies the end of an Ethernet frame. Following the transmission of the FCS,
the Ethernet controller writes the frame status bits into the BD and clears TxBD[R]. If the end of the
current buffer is reached and TxBD[L] is cleared (a frame is comprised of multiple buffer descriptors),
only TxBD[R] is cleared.
For both half- and full-duplex modes, an interrupt can be issued depending on TxBD[I]. The Ethernet
controller then proceeds to the next TxBD in the table. In this way, the core can be interrupted after each
frame, after each buffer, or after a specific buffer is sent. If TxBD[PAD/CRC] is set, the Ethernet controller
pads any frame shorter than 64 bytes with zero bytes to make up the minimum length.
To pause transmission, or rearrange the transmit queue, set DMACTRL[GTS]. This can be useful for
transmitting expedited data ahead of previously-linked buffers or for error situations. If this bit is set, the
eTSEC transmitter performs a graceful transmit stop. The Ethernet controller stops immediately if no
transmission is in progress or continues transmission until all queued frames in the Tx FIFO have been
disposed of. The IEVENT[GTSC] interrupt occurs once the graceful transmit stop operation is completed.
After the DMACTRL[GTS] is cleared, the eTSEC resumes transmission with the next frame.
While the eTSEC is in 10/100Mbps mode it sends bytes least-significant nibble first and each nibble is
sent lsb first. While it is in 1000Mbps mode it sends bytes LSB first.
15.6.2.4

Gigabit Ethernet Frame Reception

The eTSEC Ethernet receiver is designed to work with little core intervention and can perform data
extraction, address recognition, CRC checking, short frame checking, and maximum frame-length
checking.
After a hardware reset, the software driver clears the RSTAT register and sets MACCFG1[RX_EN]. The
Ethernet receiver is enabled and immediately starts processing receive frames. The MAC checks for when
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
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