Freescale Semiconductor MPC8313E Family Reference Manual page 917

Ethernet packet by centralizing status information for the data packet in the status field of the BD and by
containing a data BD pointer to the location of the data buffer. Software is responsible for setting up the
BDs in memory. Because of pre-fetching, a minimum of four buffer descriptors per ring are required. This
applies to both the transmit and the receive descriptor rings. Transmit rings are limited to a maximum size
of 65536 BDs due to BD and frame data prefetching. Software also must have the data pointer pointing to
a legal memory location. Within the status field, there exists an ownership bit which defines the current
state of the buffer (pointed to by the data pointer). Other bits in the status field of the buffer descriptor are
used to communicate status/control information between the eTSEC and the software driver.
Because there is no next BD pointer in the transmit/receive BD (see
sequentially in memory. The eTSEC increments the current BD location appropriately to the next BD
location to be processed. There is a wrap bit in the last BD that informs the eTSEC to loop back to the
beginning of the BD chain. Software must initialize the TBASE and RBASE registers that point to the
beginning transmit and receive BDs for eTSEC.
Memory Map
TxBD Table
Pointer
(TBASE n )
RxBD Table
Pointer
(RBASE n )
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
System Memory
Table for Ring n
Table for Ring n
Figure 15-147. Example of eTSEC Memory Structure for BDs
Figure
TxBD
Tx Buffer
RxBD
Rx Buffer
Enhanced Three-Speed Ethernet Controllers
15-148), all BDs must reside
Tx Buffer Descriptors
Status & Control
Data Length
Buffer Pointer
Rx Buffer Descriptors
Status & Control
Data Length
Buffer Pointer
15-187