Freescale Semiconductor MPC8313E Family Reference Manual page 460

Enhanced Local Bus Controller
Table 10-2. Enhanced Local Bus Controller Detailed Signal Descriptions (continued)
Signal I/O
LWE0/ O GPCM write enable 0/FCM write enable/UPM byte select 0. These signals select or validate each byte
LFWE/ lane of the data bus. For an 8-bit port size, bit 0 is the only defined signal. The least-significant address
LBS0, bits of each access also determine which byte lanes are considered valid for a given data transfer.
LWE1/
State
LBS1
Meaning
Timing Assertion/Negation—See
LGPL0/ O General purpose line 0/FCM command latch enable.
LFCLE
State
Meaning
LGPL1/ O General-purpose line 1/FCM address latch enable.
LFALE
State
Meaning
LOE/LGPL2/ O GPCM output enable/General-purpose line 2/FCM read enable.
LFRE
State
Meaning
LGPL3/ O General-purpose line 3/FCM write protect.
LFWP
State
Meaning
LGTA/LGPL4/ I/O GPCM transfer acknowledge/General-purpose line 4/FCM Flash ready-busy/UPM wait.
LFRB/
State
LUPWAIT
Meaning
LGPL5 O General-purpose line 5
State
Meaning
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
10-6
Asserted/Negated—For GPCM operation, LWE[0:1] assert for each byte lane enabled for
writing.
LFWE enables command, address, and data writes to NAND Flash EEPROMs controlled
by FCM.
LBS[0:1] are programmable byte-select signals in UPM mode. See
"RAM Array," for programming details about LBS[0:1].
Section 10.4.2, "General-Purpose Chip-Select Machine
for details regarding the timing of LWE[0:1].
Asserted/Negated—In UPM mode, LGPL0 is one of six general purpose signals; it is driven
with a value programmed into the UPM array.
In FCM mode, LFCLE enables command cycles to NAND Flash EEPROMs.
Asserted/Negated—In UPM mode, LGPL1 is one of six general purpose signals; it is driven
with a value programmed into the UPM array.
In FCM mode, LFALE enables address cycles to NAND Flash EPROMs.
Asserted/Negated—Controls the output buffer of memory when accessing memory/devices in
GPCM mode.
In UPM mode, LGPL2 is one of six general purpose signals; it is driven with a value
programmed into the UPM array.
LFRE enables data read cycles from NAND Flash EEPROMs controlled by FCM.
Asserted/Negated—In UPM mode, LGPL3 is one of six general purpose signals; it is driven
with a value programmed into the UPM array.
In FCM mode LFWP protects NAND Flash EEPROMs from accidental erasure and
programming when LFWP is asserted low—see
Register (FMR)," for programming of FCM operations to control LFWP.
Asserted/Negated—Input in GPCM or FCM modes used for transaction termination. It may
also be configured as one of six general-purpose output signals when in UPM mode or
as an input to force the UPM controller to wait for the memory/device. FCM uses LFRB
to stall during long-latency read and programming operations, continuing once LFRB
returns high.
Asserted/Negated—One of six general purpose signals when in UPM mode, and drives a
value programmed in the UPM array.
Description
Section 10.3.1.17, "Flash Mode
Section 10.4.4.4,
(GPCM),"
Freescale Semiconductor