Boot Memory Space - Freescale Semiconductor MPC8313E Family Reference Manual

Revision History
0x2_314C FRINDEX—USB frame index
0x2_3154 PERIODICLISTBASE—Frame list base address
0x2_31A4 OTGSC—On-the-Go status and control
0x2_31AC ENDPTSETUPSTAT—Endpoint setup status
0x2_4730 CAR1—Carry register one register
0x2_4734 CAR2—Carry register two register
Chapter 3, throughout Relabeled MA[0:14] to MA[14:0].
3.1, 3-3
4.3.3.1, 4-21
4.3.3.3, 4-27
Bits Name
0 PCIHOST
1 Reserved
2 PCIARB
3 Reserved
4 COREDIS
5 BMS
6–7 BOOTSEQ
8 SWEN
9–11 ROMLOC
12–13 RLEXT
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
A-2
In addition, modify the rows for the following registers:
In Figure 3-2, "MPC8313E Signal Groupings (2 of 2)," remove USB_PHY_GND,
M1LALE, and M2LALE signals.
In addition, add the following signals to Figure 3-2, "MPC8313E Signal
Groupings (2 of 2)":
SDAVDD
SDAVSS
SD_PLL_TPA_ANA
SD_PLL_TPD
Add the following sentence at the end of the first paragraph:
"+ LCS0 is the default for GPCM, so GPCM controlled is used to read the reset
configuration word from EEPROM. /LGTA should be high to avoid unintended
early termination of the read cycle."
In Table 4-24, "Hard-Coded Reset Configuration Word High Field Values," add
CFG_RESET_SOURCE[0:3] = 1011 column; update 1100 TSEC1M and
TSEC2M values as follows:
Field Values when
CFG_RESET_SOURCE[0:3] = 1000–1100
1000 1001 1010
0
1
0
0
1
1
00
0
000
00
R/W
R/W
Mixed
w1c
w1c
w1c
1011 1100
PCI agent mode
—
External arbiter is used
—
e300 core is disabled (boot holdoff)
Boot memory space is 0xFF80_0000–
0xFFFF_FFFF. MSR[IP] initial value is 0b1.
Boot sequencer is disabled.
Software watchdog disabled.
Boot ROM interface location.
Legacy mode.
All zeros 16.3.2.4/1616-18
All zeros 16.3.2.6/1616-19
0x0000_1030 16.3.2.15/1616-31
0x0000_0000 16.3.2.17/16-35
0x0000_0000 15.5.3.6.44/15-101
0x0000_0000 15.5.3.6.45/15-103
Meaning
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