Address Compare—Implementation Details; Arbitration Procedure - Freescale Semiconductor MPC8313E Family Reference Manual

• Slave mode
— Acknowledging address match
— Data bit (transmit)
— ACK bit (receive)
The SCLn signal corresponds to the internal SCLn signal when one or more of the following conditions
are true in either master or slave mode:
• Master mode
— Bus owner
— Lost arbitration
— START condition
— STOP condition
— Repeated START condition begin
— Repeated START condition end
• Slave mode
— Address cycle
— Transmit cycle
— ACK cycle
17.4.1.6 Address Compare—Implementation Details
The address compare block determines whether a slave has been properly addressed, either by its slave
address or by the general broadcast address (which addresses all slaves). The following address
comparisons are performed:
• Whether a broadcast message has been received, to update I2CnSR
• Whether the module has been addressed as a slave, to update I2CnSR and to generate an interrupt
• Whether the address transmitted by the current master matches the general broadcast address
17.4.2

Arbitration Procedure

2
The I C interface is a true multiple-master bus. If two or more masters simultaneously try to control the
bus, each master's clock synchronization procedure (including the I
clock—the low period is equal to the longest clock-low period and the high is equal to the shortest one
among the masters. A bus master loses arbitration if it transmits a logic 1 on SDAn while another master
transmits a logic 0. The losing masters immediately switch to slave-receive mode and stop driving the
SDAn line. In this case, the transition from master to slave mode does not generate a STOP condition.
2
Meanwhile, the I C unit sets I2CnSR[MAL] to indicate the loss of arbitration and, as a slave, services the
transaction if it is directed to itself.
2
If the I C module is enabled in the middle of an ongoing byte transfer, the interface behaves as follows:
• Slave mode—the I
a subsequent START condition is detected.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
2
C module ignores the current transfer on the bus and starts operating whenever
2
C module) determines the bus
2
I C Interfaces
17-13