Freescale Semiconductor MPC8313E Family Reference Manual page 743

eTSEC1
Offset
0x2_4008– Reserved
0x2_400C
0x2_4010 IEVENT—Interrupt event register
0x2_4014 IMASK—Interrupt mask register
0x2_4018 EDIS—Error disabled register
0x2_401C Reserved
0x2_4020 ECNTRL—Ethernet control register
0x2_4024 Reserved
0x2_4028 PTV—Pause time value register
0x2_402C DMACTRL—DMA control register
0x2_4030 Reserved TBIPA—TBI PHY address register
0x2_4034– Reserved
0x2_40FC
0x2_4100 TCTRL—Transmit control register
0x2_4104 TSTAT—Transmit status register
0x2_4108 DFVLAN*—Default VLAN control word
0x2_410C Reserved
0x2_4110 TXIC—Transmit interrupt coalescing register
0x2_4114 TQUEUE*—Transmit queue control register
0x2_4118– Reserved
0x2_413C
0x2_4140 TR03WT*—TxBD Rings 0–3 round-robin weightings
0x2_4144 TR47WT*—TxBD Rings 4–7 round-robin weightings
0x2_4148– Reserved
0x2_4180
0x2_4180 TBDBPH*—Tx data buffer pointer high bits
0x2_4184 TBPTR0—TxBD pointer for ring 0
0x2_4188 Reserved
0x2_418C TBPTR1*—TxBD pointer for ring 1
0x2_4190 Reserved
0x2_4194 TBPTR2*—TxBD pointer for ring 2
0x2_4198 Reserved
0x2_419C TBPTR3*—TxBD pointer for ring 3
0x2_41A0 Reserved
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 15-4. Module Memory Map (continued)
1
Name
eTSEC Transmit Control and Status Registers
Enhanced Three-Speed Ethernet Controllers
2
Access Reset
— —
w1c All zeros
R/W All zeros
R/W All zeros
— —
R/W All zeros
— —
R/W All zeros
R/W All zeros
—R/W —All zeros
— —
R/W All zeros
w1c All zeros
R/W 0x8100_0000
— —
R/W All zeros
R/W 0x0000_8000
— —
R/W All zeros
R/W All zeros
— —
R/W All zeros
R/W All zeros
— —
R/W All zeros
— —
R/W All zeros
— —
R/W All zeros
— —
Section/Page
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15.5.3.1.3/15-24
15.5.3.1.4/15-28
15.5.3.1.5/15-30
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15.5.3.1.6/15-31
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15.5.3.1.7/15-33
15.5.3.1.8/15-34
—15.5.3.1.9/15-35
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15.5.3.2.1/15-36
15.5.3.2.2/15-38
15.5.3.2.3/15-42
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15.5.3.2.4/15-43
15.5.3.2.5/15-44
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15.5.3.2.6/15-44
15.5.3.2.7/15-45
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15.5.3.2.8/15-46
15.5.3.2.9/15-46
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15.5.3.2.9/15-46
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15.5.3.2.9/15-46
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15.5.3.2.9/15-46
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15-13