Port State And Control - Freescale Semiconductor MPC8313E Family Reference Manual

Recommended: enable all device interrupts including: USBINT, USBERRINT, Port Change
Detect, USB Reset Received, DCSuspend.
For a list of available interrupts refer to the USBINTR and the USBSTS register tables.
8. Set USBCMD[RS] to run mode.
After the run bit is set, a device reset will occur. The DCD must monitor the reset event and set the
DEVICEADDR register, set the ENDPTCTRLx registers, and adjust the software state as
described in Section 16.8.2.1, "Bus Reset."
Endpoint 0 is designed as a control endpoint only and does not need to be
configured using ENDPTCTRL0 register.
It is also not necessary to initially prime Endpoint 0 because the first packet received will always be a setup
packet. The contents of the first setup packet will require a response in accordance with USB device
framework command set.
16.8.2

Port State and Control

From a chip or system reset, the USB_DR enters the powered state. A transition from the powered state to
the attach state occurs when the run/stop bit (USBCMD[RS]) is set to a '1'. After receiving a reset on the
bus, the port will enter the defaultFS or defaultHS state in accordance with the protocol reset described in
Appendix C.2 of the USB Specification Rev. 2.0.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
NOTE
Figure 16-63 depicts the state of a USB 2.0 device.
Universal Serial Bus Interface
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