Periodic Interval Timer Event Register (Ptevr); Periodic Interval Timer Unit - Freescale Semiconductor MPC8313E Family Reference Manual

System Configuration
5.6.5.5

Periodic Interval Timer Event Register (PTEVR)

The periodic interval timer event register (PTEVR), shown in
the interrupts. The register can be read at any time.
PTEVR bits are cleared by writing ones. Writing zeros does not affect the value of the status bits.
Offset 0x10
0
R
W
Reset
Table 5-52 defines the bit fields of PTEVR.
Bits Name
0–30 — Write reserved, read = 0
31 PIF Periodic interrupt flag bit. It is asserted after the SPMPIT counter counts to zero. This status bit should be
cleared by software.
5.6.6 Functional Description
5.6.6.1

Periodic Interval Timer Unit

The PIT generates periodic interrupts for use with a real-time operating system or the application software.
It consists of a 32-bit down-counter which is decremented by a clock derived from the CSB clock or from
the PIT clock. The 32-bit counter decrements to zero when loaded with a initial value from the periodic
interval timer load register (PTLDR). After the timer reaches zero, PTEVR[PIF] is set and an interrupt is
generated if PTCNR[PIM] = 1. At the next count cycle, the value in the PTLDR[CLDV] is loaded into the
counter and the process repeats. When a new value is loaded into the PTLDR[CLDV], the PIT is updated,
the prescaler counter is reset, and the counter begins counting. Setting of PTEVR[PIF] generates an
interrupt, that remains pending until PTEVR[PIF] is cleared. If PTEVR[PIF] is set again before being
cleared, the interrupt remains pending until PTEVR[PIF] is cleared. Any write to the PTLDR[CLDV] stops
the current countdown and the count resumes with the new value in PTLDR[CLDV]. If
PTCNR[CLEN] = 0, the PIT cannot count and retains the old count value. PTCTR contain the PIT current
value. The PIT function can be disabled if needed.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
5-48
Figure 5-37. Periodic Interval Timer Event Register (PTEVR)
Table 5-52. PTEVR Bit Settings
Figure 5-37, is used to report the source of
—
All zeros
Description
Access: w1c
30 31
PIF
w1c
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