Freescale Semiconductor MPC8313E Family Reference Manual page 354

e300 Processor Core Overview
Although interrupts have other characteristics, such as whether they are maskable, the distinctions shown
in Table 7-6 define categories of interrupts that the core handles uniquely. Note that
synchronous, imprecise instructions. While the PowerPC architecture supports imprecise handling of
floating-point exceptions, the core implements floating-point exception modes as precise.
The e300 core interrupts and exception conditions that cause them are listed in
Vector Offset
Interrupt Type
(hex)
Reserved 00000
System reset 00100
Machine check 00200
DSI 00300
ISI 00400
External interrupt 00500
Alignment 00600
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
7-32
Table 7-7. Exceptions and Interrupts
Caused by the assertion of either hreset.
Caused by the assertion of the tea signal during a data bus transaction, assertion of mcp ,
an address or data parity error, or an instruction or data cache parity error. Note that the
e300 has SRR1 register values that are different from the G2/G2_LE cores' when a
machine check occurs.
Determined by the bit settings in the DSISR, listed as follows:
1 Set if the translation of an attempted access is not found in the primary hash table entry
group (HTEG), or in the rehashed secondary HTEG, or in the range of a DBAT register;
otherwise cleared
4 Set if a memory access is not permitted by the page or DBAT protection mechanism;
otherwise cleared
6 Set for a store operation and cleared for a load operation
9 Set if a data address breakpoint interrupt occurs when the data [0–28] in the DABR or
DABR2 matches the next data access (load or store instruction) to complete in the
completion unit. The different breakpoints are enabled as follows:
• Write breakpoints enabled when DABR[30] is set
• Read breakpoints enabled when DABR[31] is set
Caused when an instruction fetch cannot be performed for any of the following reasons:
• The effective (logical) address cannot be translated. That is, there is a page fault for this
portion of the translation, so an ISI interrupt must be taken to load the PTE (and possibly
the page) into memory.
• The fetch access violates memory protection (indicated by SRR1[4] set). If the key bits
(Ks and Kp) in the segment register and the PP bits in the PTE are set to prohibit read
access, instructions cannot be fetched from this location.
Caused when MSR[EE] = 1 and the int signal is asserted.
Caused when the core cannot perform a memory access for any of the reasons described
below:
• The operand of a floating-point load or store instruction is not word-aligned.
• The operands of lmw, stmw, lwarx, and stwcx. instructions are not aligned.
• The instruction is lswi, lswx, stswi, stswx, and the core is in little-endian mode. Note
that PowerPC little-endian mode is not supported on the e300 core.
• The operand of dcbz is in memory that is write-through-required or caching-inhibited.
Table
Exception Conditions
—
Table 7-6 includes no
7-7.
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