Freescale Semiconductor MPC8313E Family Reference Manual page 932

Enhanced Three-Speed Ethernet Controllers
Table 15-172 describes the register initializations required to configure the eTSEC in RMII mode.
(Used to setup Reduced-Pin mode = 1, and TBIM = 0,statistics enable = 1)
set system clock divide by 14 for example to insure that MDC clock speed = < 2.5 MHz
Set up the MII Mgmt for a write cycle to external the PHY AN Advertisement register (write the PHY address and Register
The AN Advertisement register is at offset address 0x04 from the external PHY address. (in this case 0x11)
Write to MII Mgmt Control with 16-bit data intended for the external PHY AN Advertisement register,
Set up the MII Mgmt for a write cycle to the external PHY Control register (write the PHY address and Register address),
The control register is at offset address 0x00 from the external PHY address. (in this case 0x11)
Write to MII Mgmt Control with 16-bit data intended for the external PHY Control register,
This enables the external PHY to restart Auto-Negotiations using the configuration set in the AN Advertisement register.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
15-202
Table 15-172. RMII Mode Register Initialization Steps
MACCFG1[1000_0000_0000_0000_0000_0000_0000_0000]
Clear Soft_Reset,
MACCFG1[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize MACCFG2,
MACCFG2[0000_0000_0000_0000_0111_0001_0000_0101]
(I/F Mode = 1, Full Duplex = 1)
Initialize ECNTRL,
ECNTRL[0000_0000_0000_0000_0001_0000_0001_0000]
Initialize MAC Station Address
MACSTNADDR2[0110_0000_0000_0010_0000_0000_0000_0000]
to 02608C:876543 for example
Initialize MAC Station Address
MACSTNADDR1[0100_0011_0110_0101_1000_0111_1000_1100]
to 02608C:876543 for example
Setup the MII Mgmt clock speed,
MIIMCFG[0000_0000_0000_0000_0000_0000_0000_1101]
Read MII Mgmt Indicator register and check for Busy = 0,
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
This indicates that the eTSEC MII Mgmt bus is idle.
MIIMADD[0000_0000_0000_0000_0001_0001_0000_0100]
Perform an MII Mgmt write cycle to the external PHY.
MIIMCON[0000_0000_0000_0000_u0uu_uuuu_uuuu_uuuu]
Where u must be selected by the user for proper system configuration.
Check to see if MII Mgmt write is complete.
Read MII Mgmt Indicator register and check for Busy = 0,
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
This indicates that the write cycle was completed.
MIIMADD[0000_0000_0000_0000_0001_0001_0000_0000]
Perform an MII Mgmt write cycle to the external PHY.
MIIMCON[0000_0000_0000_0000_0001_0010_0000_0000]
Check to see if MII Mgmt write is complete.
Read MII Mgmt Indicator register and check for Busy = 0,
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
This indicates that the write cycle was completed.
Set Soft_Reset,
address),
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