Reduced Ten-Bit Interface (Rtbi) - Freescale Semiconductor MPC8313E Family Reference Manual

Powerquicc ii pro integrated processor

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Enhanced Three-Speed Ethernet Controllers

The management signals (MDC and MDIO) are common to all of the gigabit Ethernet controllers module

connections in the system, assuming that each PHY has a different management address.

Reduced Ten-Bit Interface (RTBI)

This section describes the reduced ten-bit interface (RTBI) intended to be used between the PHYs and the

eTSEC to implement a reduced-pin count version of a SerDes interface for optical-fiber devices in

1000BASE-SX/LX applications.

signals required to establish eTSEC module connection with a PHY. Note that in RTBI the eTSEC

immediately begins auto-negotiation with the SerDes.

MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3

Gigabit Reference Clock (GTX_CLK125)

Gigabit Transmit Clock (TSEC n _GTX_CLK)

Transmit Control (TX_EN/f(TX_EN,TX_ER))

Transmit Data (TSECn_TXD[3:0]

Receive Clock (TSEC n _RX_CLK)

Receive Control (RX_DV/f(RX_DV,RX_ER))

Receive Data (TSECn_RXD[3:0]

Management Data Clock

Management Data I/O

Figure 15-131. eTSEC-RGMII Connection

Figure 15-132

depicts the basic components of the RTBI including the

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