An Link Partner Base Page Ability Register (Anlpbpa) - Freescale Semiconductor MPC8313E Family Reference Manual

15.5.4.3.4

AN Link Partner Base Page Ability Register (ANLPBPA)

Figure 15-122 describes the definition for the ANLPBPA register.
Offset 0x05
0 1
R Next Page
—
W
Reset
Figure 15-122. AN Link Partner Base Page Ability Register Definition
Table 15-130 describes the fields of the ANLPBPA register.
Bits Name
0 Next Page Next page. This bit is read-only. The link partner sets or clears this bit.
0 Link partner has no subsequent next pages or is not capable of receiving next pages.
1 Link partner either requesting next page transmission or indicating the capability to receive next pages.
1 — Reserved. (Ignore on read)
2–3 Remote The link partner's remote fault condition is encoded in bits 2 and 3 of the base page. Values are shown in
Fault the remote fault encoding field table below. This bit is read-only.
4–6 — Reserved, should be cleared.
7–8 Pause Encoding of the link partner's PAUSE capability is shown in the PAUSE encoding table below. For priority
resolution information consult. This bit is read-only
PAUSE bit[8]
9 Half Half-duplex capability. This bit is read-only.
Duplex 0 Link partner is not capable of half-duplex mode.
1 Link partner is capable of half-duplex mode.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
2 3 4
Remote Fault
—
Table 15-130. ANLPBPA Field Descriptions
RF1 bit[3] RF2 bit[2]
0 0
0 1
1 0
1 1
ASM_DIR bit[7]
0 0
0 1
1 0
1 1
6 7 8 9
Pause Half Duplex Full Duplex
All zeros
Description
Description
No error, link OK
Offline
Link_Failure
Auto-Negotiation_Error
Capability
No PAUSE
Asymmetric PAUSE toward link partner
Symmetric PAUSE
Both symmetric PAUSE and
Asymmetric PAUSE toward local device
Enhanced Three-Speed Ethernet Controllers
Access: Read/Write
10 11 15
—
15-129