Freescale Semiconductor MPC8313E Family Reference Manual page 851

Powerquicc ii pro integrated processor

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15.5.3.10.13 Timer Fixed Interval Period Register (TMR_FIPER1–3)

Timer fixed interval period pulse generator register. It is used to generate periodic pulses. This register is

reset with 0xFFFF_FFFF to prevent any false pulse upon initialization. The down count register loads the

value programmed in the fixed period interval (FIPER). FIPER register must be programmed before the

timer is enabled. At every tick of the timer accumulator overflow, the counter decrements by the value of

TMR_CTRL[TCLK_PERIOD]. It generates a pulse when the down counter value reaches zero. It reloads

the down counter in the cycle following a pulse.

Should a user wish to use the TMR_FIPER1 register to generate a 1 PPS event, the following setup should

Program TMR_FIPER1 to a value that will generate a pulse every second,

Program TMR_ALARM1 to the correct time for the first PPS event

Enable the timer

The eTSEC will then wait for TMR_ALARM1 to expire before enabling the count down of

TMR_FIPER1. The end result will be that TMR_FIPER1 will pulse every second after the original timer

ALARM1 expired.

In the case where the PPS signals are required to be phased aligned to the prescale output clock, the alarm

value should be configured to 1 clock period less than the wanted value.

In order to keep tracking the prescale output clock, each time before enabling the FIPER, the user must

reset the FIPER by writing a new value to the register. The ratio between the prescale register value and

the FIPER value should be devisable by the clk period.

FIPER_VALUE = (prescale_value × tclk_per × N) – tclk_per

For example:

prescale = 9

clock period = 10

The FIPER can get the following values: 80, 170, 260 .......

The three registers in eTSEC1 are shared for all eTSECs.

TMR_FIPER register.

Offset eTSEC1:0x2_4E80+4* n

MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3

Freescale Semiconductor

Figure 15-117. TMR_FIPER n Register Definition

Figure 15-117

Enhanced Three-Speed Ethernet Controllers

describes the definition for the

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