Freescale Semiconductor MPC8313E Family Reference Manual page 71

Table
Number
16-37 CONTROL Field Descriptions ........................................................................................... 16-44
16-38 Supported PHY Interfaces .................................................................................................. 16-46
16-39 Typ Field Encodings ........................................................................................................... 16-49
16-40 Next Schedule Element Pointer .......................................................................................... 16-50
16-41 iTD Transaction Status and Control.................................................................................... 16-51
16-42 Buffer Pointer Page 0 (Plus) ............................................................................................... 16-52
16-43 iTD Buffer Pointer Page 1 (Plus) ........................................................................................ 16-52
16-44 Buffer Pointer Page 2 (Plus) ............................................................................................... 16-52
16-45 Buffer Pointer Page 3–6 ...................................................................................................... 16-52
16-46 Next Link Pointer................................................................................................................ 16-53
16-47 Endpoint and Transaction Translator Characteristics ......................................................... 16-54
16-48 Micro-Frame Schedule Control .......................................................................................... 16-54
16-49 siTD Transfer Status and Control........................................................................................ 16-54
16-50 siTD Buffer Pointer Page 0 (Plus) ...................................................................................... 16-55
16-51 siTD Buffer Pointer Page 1 (Plus) ...................................................................................... 16-56
16-52 siTD Back Link Pointer ...................................................................................................... 16-56
16-53 qTD Next Element Transfer Pointer (DWord 0) ................................................................. 16-57
16-54 qTD Alternate Next Element Transfer Pointer (DWord 1) ................................................. 16-57
16-55 qTD Token (DWord 2) ........................................................................................................ 16-58
16-56 qTD Buffer Pointer ............................................................................................................. 16-61
16-57 Queue Head DWord 0 ......................................................................................................... 16-62
16-58 Endpoint Characteristics: Queue Head DWord 1................................................................ 16-63
16-59 Endpoint Capabilities: Queue Head DWord 2 .................................................................... 16-64
16-60 Current qTD Link Pointer ................................................................................................... 16-65
16-61 Host-Controller Rules for Bits in Overlay (DWords 5, 6, 8, and 9) ................................... 16-66
16-62 FTSN Normal Path Pointer ................................................................................................. 16-67
16-63 FSTN Back Path Link Pointer ............................................................................................ 16-67
16-64 Behavior During Wake-Up Events...................................................................................... 16-71
16-65 Operation of FRINDEX and SOFV (SOF Value Register)................................................. 16-76
16-66 Example Periodic Reference Patterns for Interrupt Transfers ............................................ 16-89
16-67 Ping Control State Transition Table .................................................................................... 16-90
16-68 Interrupt IN/OUT Do Complete Split State Execution Criteria........................................ 16-104
16-69 Initial Conditions for OUT siTD TP and T-Count Fields ................................................. 16-112
16-70 Transaction Position (TP)/Transaction Count (T-Count) Transition Table....................... 16-112
16-71 Summary siTD Split Transaction State............................................................................. 16-116
16-72 Example Case 2a—Software Scheduling siTDs for an IN Endpoint................................ 16-117
16-73 Summary of Transaction Errors ........................................................................................ 16-120
16-74 Summary Behavior on Host System Errors ...................................................................... 16-123
16-75 Endpoint Capabilities/Characteristics ............................................................................... 16-125
16-76 Current dTD Pointer.......................................................................................................... 16-126
16-77 Multiple Mode Control ..................................................................................................... 16-127
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Tables
Tables
Title
Page
Number
lxxi