Fcm Ready/Busy Timing - Freescale Semiconductor MPC8313E Family Reference Manual

An example of minimum delay command timing appears in
and hold timing of command, address, and write data cycles with respect to LFWE assertion are all
identical, and that the minimum cycle extends for two LCLK clock cycles.
LCLK
(unused)
LFCLE
LFALE
LFWE
LAD[0:7]
TA
Figure 10-52. Example of FCM Command and Address Timing with Minimum Delay Parameters
An example of relaxed command timing is shown in
LCLK
(unused)
LFCLE
LFALE
LFWE
LAD[0:7]
TA
Figure 10-53. Example of FCM Command and Address Timing with Relaxed Parameters
10.4.3.3.3

FCM Ready/Busy Timing

Instructions CW0, CW1, RBW, and RSW force FCM to observe the state of the LFRB pin, which may be
driven low by a long-latency NAND Flash operation, such as a page read. Following the issue of such
commands, FCM waits as shown in
observing LFRB before it has been properly driven low by the device, but does not preclude LFRB from
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
command
(for TRLX = 0, CHT = 0, CST = 0, SCY = 0, CLKDIV = 4*N)
2×SCY = 4 cycles
command
(for TRLX = 1, CHT = 0, CST = 1, SCY = 2, CLKDIV = 4*N)
Figure 10-54
Figure 10-52. Note that the set-up, wait-state,
address 0 address 1
Figure 10-53.
before sampling the state of LFRB. This guards against
Enhanced Local Bus Controller
address 2
address
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