Boot Sequencer Done Indication; Interrupt Service Routine Flowchart - Freescale Semiconductor MPC8313E Family Reference Manual

17.4.5.4

Boot Sequencer Done Indication

Dedicated hardware is not provided to indicate whether the boot sequencer operation completed
successfully. It is recommended to use one of the GPIO signals for that purpose. To do this, the last register
preload programmed into the EEPROM should contain the address of the appropriate GPIO register and
data that causes the setting of the required GPIO signal. The GPIO signal may be used for an external
device or for debug purposes.
17.5 Initialization/Application Information
This section describes some programming guidelines recommended for the I
a recommended flowchart for I
A sync assembly instruction must be executed after each I
register accesses occur in order.
2
The I C controller does not guarantee its recovery from all illegal I
malfunctioning device may hold the bus captive. A good programming practice is for software to rely on
a watchdog timer to help recover from I
2
when the illegal I C bus behavior causes the status bits returned after an interrupt to be inconsistent with
what was expected.
17.5.1

Interrupt Service Routine Flowchart

Figure 17-11 shows an example algorithm for an I
flowchart may result in unpredictable I
the interrupt service routine may need to set I2CnCR[TXAK] when the next-to-last byte is to be accepted.
It is recommended that a sync instruction follow each I
accesses occur in order.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
2
C interrupt service routines.
2
C bus hangs. The recovery routine should also handle the case
2
C interrupt service routine. Deviation from the
2
C bus behavior. However, in the slave receive mode (not shown),
2
C interface.
2
C register read/write access to guarantee that
2
C bus activity. In addition, a
2
C register read or write to guarantee that register
2
I C Interfaces
Figure 17-11 is
17-19