Freescale Semiconductor MPC8313E Family Reference Manual page 988

Universal Serial Bus Interface
Table 16-37. CONTROL Register Field Descriptions (continued)
Bits Name
16–18 —
19–20 CLKIN_SEL[1:0] Select the clock source for the UTMI PHY PLL reference clock. The reference clock can be
21 PHY_CLK_SEL
22 UTMI_PHY_EN
23 PLL_RESET
24–25 REFSEL[1:0]
26 OTG_PORT
27 KEEP_OTG_ON Keeps the OTG comparators on during low power suspend.
28 LSF_EN
29 USB_EN
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
16-46
Reserved, must be cleared.
sourced from the USBDR_CLK or divide by 1 or 2 of the SYS_CLK. These bits are not relevant
when in ULPI mode.
00 Reference clock is USBDR_CLK
01 Reference clock is USBDR_CLK
10 Reference clock is SYS_CLK
11 Reference clock is SYS_CLK divided by 2
Select the source of the USB link controller transceiver clock. When cleared the UTMI PHY is the
source of the clock. When set, the clock is sourced from the external ULPI PHY.
0 UTMI is clock source
1 ULPI is clock source
Enable the UTMI PHY. The UTMI PHY is reset when placed in the disable mode.
0 UTMI PHY disabled
1 UTMI PHY enabled
Reset the UTMI PHY PLL. This bit is not self clearing and must be cleared to complete the reset
sequence.
0 UTMI PHY in normal operating state
1 Put UTMI PHY in reset state
The REFSEL signals are used to set the frequency value for the UTMI PLL reference clock. These
bit fields are not relevant if not in UTMI mode.
00 Reserved
01 Reference clock frequency is 24 MHz. This is the default frequency.
10 Reference clock frequency is 48 MHz
11 Reserved
Enables the OTG comparators.
0 OTG comparators disabled
1 OTG comparators enabled
0 OTG comparators disabled during suspend
1 OTG comparators enabled during suspend
This bit is used to enable the UTMI line state filter. When enabled the UTMI linestate[1:0] output
of the UTMI PHY are filtered to account for any skew between the USB differential data lines
(DP/DM).
0 Line state filter disabled
1 Line state filter enabled
UTMI mode: This bit is used to enable the USB interface. It must be set before setting RS bit in
USB CMD register.
1 Enable
0 Disable
ULPI mode: In safe mode, all USB interface signals are put into input mode or driven inactive,
except for SUSPEND_STP, which is driven high. Also, the input signal DIR is forced to appear high
to the controller. This prevents any start-up problems that otherwise could occur if the PHY and
the controller take significantly different times to complete power-on reset.
1 Normal operation
0 Safe mode
Description
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