Freescale Semiconductor MPC8313E Family Reference Manual page 199

Figure 4-7 shows the internal distribution of clocks within the device.
USB_CLK_IN
USB_CR_CLK_IN
Crystal
USB_CR_CLK_OUT
CFG_CLKIN_DIV
SYS_CLK_IN
SYS_CR_CLK_IN
Crystal
SYS_CR_CLK_OUT
eTSEC
GTX_CLK125
125-MHz source
Protocol
Converter
SGMII PHY
Interface
SD_REF_CLK/
PLL
SD_REF_CLK
125-MHz source
The primary clock input to this device is PCI_CLK. This clock is the reference to the system APLL.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
MPC8313E
e300c3 core
USB Mac
USB PHY
PLL
mux
csb_clk
Clock
Unit
System
/1,/2
PLL
PCI Clock
Divider (÷2)
PMC
Figure 4-7. Clock Subsystem Block Diagram
core_clk
Core PLL
to DDR
memory
controller
DDR
Clock
Divider
/2
ddr_clk
lbc_clk
/n
To local bus
LBC
Clock
Divider
csb_clk to rest
of the device
1
0
RTC
Sys Ref
Reset, Clocking, and Initialization
MEMC_MCK
MEMC_MCK
Local Bus
LCLK[0:1]
Memory
Device
PCI_CLK/
PCI_SYNC_IN
PCI_SYNC_OUT
3
PCI_CLK_OUT[0:2]
RTC_CLK (32 kHz)
DDR
Memory
Device
4-29