Timer Ptp Packet Event Register (Tmr_Pevent) - Freescale Semiconductor MPC8313E Family Reference Manual

Table 15-112 describes the fields of the TMR_TEMASK register fields for the timer.
Bits Name
0–5 — Reserved
6 ETS2EN External trigger 2 timestamp sample event enable
7 ETS1EN External trigger 1 timestamp sample event enable
8–13 — Reserved
14 ALM2EN Timer ALM1 event enable
15 ALM1EN Timer ALM2 event enable
16–23 — Reserved
24 PP1EN Periodic pulse event 1 enable
25 PP2EN Periodic pulse event 2 enable
26–31 — Reserved

15.5.3.10.4 Timer PTP Packet Event Register (TMR_PEVENT)

The eTSEC precision timer logic can generate interrupts upon the capture of a timestamp due to either
transmission or reception of a frame. If an event occurs and its corresponding enable bit is set in the event
mask register (PEMASK), the event also causes a hardware interrupt at the PIC. A bit in the timer event
register is cleared by writing a 1 to that bit position.
TMR_PEVENT register.
Offset eTSEC1:0x2_4E0C
0
R
W
Reset
16
R
W
Reset
Table 15-113 describes the fields of the TMR_PEVENT register fields for the timer.
Bits Name
0–21 — Reserved
22 TXP2 Indicates that a PTP frame has been transmitted and its timestamp is stored in TXTS2 register.
0 PTP packet not transmitted
1 PTP packet has been transmitted
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 15-112. TMR_TEMASK Register Field Descriptions
21
—
Figure 15-109. TMR_PEVENT Register Definition
Table 15-113. TMR_PEVENT Register Field Descriptions
Enhanced Three-Speed Ethernet Controllers
Description
Figure 15-109 describes the definition for the
—
All zeros
22 23 24
TXP2 TXP1
All zeros
Description
Access: Read/Write
15
30 31
— RXP
15-115