Freescale Semiconductor MPC8313E Family Reference Manual page 124

Memory Map
Offset
0x0_856C Reserved, should be cleared
0x0_8570 PIBAR0—PCI inbound base address register 0
0x0_8578 PIWAR0—PCI inbound window attributes register 0
0x0_857C– Reserved, should be cleared
0x2_2FFF
0x2_3000– Reserved, should be cleared
0x2_30FF
0x2_3100 CAPLENGTH—Capability register length
0x2_3102 HCIVERSION—Host interface version number
0x2_3104 HCSPARAMS—Host crtl. structural parameters
0x2_3108 HCCPARAMS—Host crtl. capability parameters
0x2_3120 DCIVERSION—Device interface version number
0x2_3124 DCCPARAMS—Device controller parameters
0x2_3140 USBCMD—USB command
0x2_3144 USBSTS—USB status
0x2_3148 USBINTR—USB interrupt enable
0x2_314C FRINDEX—USB frame index
0x2_3154 PERIODICLISTBASE—Frame list base address
0x2_3154 DEVICEADDR—USB device address
0x2_3158 ASYNCLISTADDR—Next asynchronous list addr (host
mode)
0x2_3158 ENDPOINT ADDR—Address at endpoint list (device
mode)
0x2_3160 BURSTSIZE—Programmable burst size
0x2_3164 TXFILLTUNING—Host TT transmit pre-buffer packet
tuning
0x2_3170 Reserved
0x2_3180 CONFIGFLAG—Configured flag register
0x2_3184 PORTSC1—Port status/control
0x2_31A4 OTGSC—On-the-Go status and control
0x2_31A8 USBMODE—USB device mode
0x2_31AC ENDPTSETUPSTAT—Endpoint setup status
0x2_31B0 ENDPOINTPRIME—Endpoint initialization
0x2_31B4 ENDPTFLUSH—Endpoint de-initialize
0x2_31B8 ENDPTSTATUS—Endpoint status
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
2-18
Table 2-2. Memory Map (continued)
Register
USB DR Controller Registers
Access Reset
— —
R/W 0x0000_0000
R/W 0x0000_0000
— —
— —
R 0x40
R 0x0100
R 0x0111_0011
R 0x0000_0006
R 0x0001
R 0x0000_0186
R/W 0x0008_ n B n 0
R/W 0x0000_0000
R/W 0x0000_0000
R/W All zeros
R/W All zeros
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_1010
R/W 0x0002_0000
— —
R 0x0000_0001
R/W 0x9C00_0000
Mixed 0x0000_1030
R/W 0x0000_0000
w1c 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R 0x0000_0000
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