Freescale Semiconductor MPC8313E Family Reference Manual page 324

e300 Processor Core Overview
System
Register
Unit
+
Integer
Unit2
/ +
*
XER
Completion
Unit
Performance Monitor
Power
Dissipation
Control
Debug/COP
JTAG Interface
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
7-2
Sequential
Fetcher
Instruction
Queue
Dispatch Unit
32-Bit
Integer
GPR File
Unit1
GP Rename
/ +
*
Registers
XER
Completes up to
SRs
two instructions
per clock
DTLB
Time Base
Counter/
Tags
Decrementer
PLL & Clock
Multiplier
Touch Load Buffer
Copy-Back Buffer
32-Bit Address Bus
64-Bit Data Bus
Figure 7-1. e300c3 Core Block Diagram
64-Bit (Two Instructions)
Branch
64-Bit
Processing
t
64-Bi
64-Bit
Instruction Unit
64-Bit (Two Instructions)
64-Bit
FPR File
Load/Store
Unit
FP Rename
Registers
+
32-Bit
D MMU
64-Bit
DBAT
Array
16-Kbyte
D Cache
Unit
CTR
CR
LR
Floating-
Point Unit
+
/
*
FPSCR
I MMU
SRs
IBAT
Array
ITLB
16-Kbyte
Tags
I Cache
Core Interface
Freescale Semiconductor