Table of Contents
Advertisement
Overview
1.2.6.1
USB Dual-Role Controller
•
Designed to comply with Universal Serial Bus Revision 2.0 Specification
•
Supports operation as a stand-alone USB host controller
— Supports USB root hub with one downstream-facing port
— Enhanced host controller interface (EHCI) compatible
•
Supports operation as a stand-alone USB device
— Supports one upstream-facing port
— Supports three programmable bidirectional USB endpoints
•
Supports high-speed (480-Mbps), full-speed (12-Mbps), and low-speed (1.5-Mbps) operations.
Low speed is only supported in host mode.
•
Supports USB on-the-go mode when using an external ULPI (UTMI+ low-pin interface) PHY,
which includes both device and host functionality
•
On-chip USB-2.0 full-/high-speed PHY with ULPI (UTMI+ low-pin interface)
•
Supports Wake-on-USB, a method for bringing the device from standby mode to full operating
mode
•
Host and device support
1.2.7
Enhanced Local Bus Controller (eLBC)
The main component of the enhanced local bus controller (eLBC) is its memory controller, which provides
a seamless interface to many types of memory devices and peripherals. The memory controller is
responsible for controlling four memory banks shared by a NAND Flash control machine (FCM), a
general-purpose chip-select machine (GPCM), and up to three user-programmable machines (UPMs). As
such, it supports a minimal glue logic interface to SRAM, EPROM, NOR Flash EPROM, NAND Flash
EPROM, Flash EPROM, burstable RAM, and other peripherals. The eLBC external address latch enable
(LALE) signal allows multiplexing of addresses with data signals to reduce the device pin count.
The enhanced local bus controller also includes a number of data checking and protection features such as
data parity generation and checking, write protection, and a bus monitor to ensure that each bus cycle is
terminated within a user-specified period.
The main features of the enhanced local bus controller (eLBC) are as follows:
•
Memory controller with four memory banks (chip selects)
— 32-bit address decoding with mask
— Variable memory block sizes (32 Kbytes to 4 Gbytes in FCM mode, 32 Kbytes to 64 Mbytes
in UPM mode, and 32 Kbytes to 64 Mbytes in GPCM mode)
— Selection of control signal generation on a per-bank basis
— Data buffer controls activated on a per-bank basis
— Up to 256-byte bursts, arbitrarily aligned
— Automatic segmentation of large transactions into memory accesses optimized for bus width
and addressing capability
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
1-14
Freescale Semiconductor
Advertisement
Chapters
Table of Contents
