Global Timers Reference Registers (Gtrfr1–Gtrfr); Global Timers Capture Registers (Gtcpr1–Gtcpr); Global Timers Counter Registers (Gtcnr1–Gtcnr) - Freescale Semiconductor MPC8313E Family Reference Manual

System Configuration
5.7.5.3 Global Timers Reference Registers (GTRFR1–GTRFR4)
Global timers reference registers, shown in
containing the 16-bit reference values for each timer's timeout. The reference value is not reached until
GTCNRn[CNV] increments to the value in GTRFRn[TRV].
Offset 0x14(GTRFR1)
0x16(GTRFR2)
0
R
W
Reset 1 1
Figure 5-43. Global Timers Reference Registers (GTRFR1–GTRFR4)
Table 5-59 defines the bit fields of GTRFR.
Bits Name
0–15 TRV Timeout reference value.
16-bit timeout reference value for the corresponding timer. Set to all ones by reset.
5.7.5.4 Global Timers Capture Registers (GTCPR1–GTCPR4)
Global timers capture registers (GTCPR1, GTCPR2, GTCPR3, and GTCPR4), shown in
used to latch the value of the counters according to GTMDRn[CE].
Offset 0x18(GTCPR1)
0x1A(GTCPR2)
0
R
W
Reset
Figure 5-44. Global Timers Capture Registers (GTCPR1–GTCPR4)
Table 5-60 defines the bit fields of GTCPRn.
Bits Name
0–15 LCV Latched counter value. Corresponding timer's 16-bit latched value.
5.7.5.5 Global Timers Counter Registers (GTCNR1–GTCNR4)
Global timers counter registers (GTCNR1, GTCNR2, GTCNR3, and GTCNR4), shown in
four 16-bit, memory-mapped, read/write up-counters. A read cycle to a GTCNRn[CNV] fields yields the
current value of the appropriate timer but does not affect the counting operation. A write cycle to a
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
5-60
Figure
0x24(GTRFR3)
0x26(GTRFR4)
1 1 1 1
Table 5-59. GTRFR Bit Settings
0x28(GTCPR3)
0x2A(GTCPR4)
Table 5-60. GTCPR n Bit Settings
5-43, are 16-bit memory-mapped, read/write registers
TRV
1 1 1 1
Description
LCV
All zeros
Description
Access: Read/Write
1 1 1 1
Figure
Access: Read only
Figure
Freescale Semiconductor
15
1 1
5-44, are
15
5-45, are