Generation Of Stop; Generation Of Repeated Start; Slave Mode Interrupt Service Routine; Slave Transmitter And Received Acknowledge - Freescale Semiconductor MPC8313E Family Reference Manual

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I C Interfaces
17.5.5

Generation of STOP

A data transfer ends with a STOP condition generated by the master device. A master transmitter can
generate a STOP condition after all the data has been transmitted.
If a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not
acknowledging the last byte of data (by setting the transmit acknowledge bit (I2CnCR[TXAK])) before
reading the next-to-last byte of data. At this time, the next-to-last byte of data has been transferred on the
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I C interface, so the last byte does not receive the data acknowledge (because I2CnCR[TXAK] is set).
Before the interrupt service routine reads the last byte of data, a STOP condition must first be generated.
17.5.6

Generation of Repeated START

At the end of a data transfer, if the master still wants to communicate on the bus, it can generate another
START condition followed by another slave address without first generating a STOP condition. This is
accomplished by setting I2CnCR[RSTA].
17.5.7 Generation of SCL n When SDA n is Negated
It is sometimes necessary to force the I
SCLn (even though SDAn may already be driven, which indicates that the bus is busy). This can occur
when a system reset does not cause all I
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I C device while this I
procedure can be used to force this I
finish its transaction:
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1. Disable the I C module and set the master bit by setting I2CnCR to 0x20.
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2. Enable the I C module by setting I2CnCR to 0xA0.
3. Read I2CnDR.
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4. Return the I C module to slave mode by setting I2CnCR to 0x80.
17.5.8

Slave Mode Interrupt Service Routine

In the slave interrupt service routine, the module addressed as a slave should be tested to check if a calling
of its own address has been received. If I2CnSR[MAAS] is set, software should set the transmit/receive
mode select bit (I2CnCR[MTX]) according to the R/W command bit (I2CnSR[SRW]). Writing to I2CnCR
clears MAAS automatically. MAAS is read as set only in the interrupt handler at the end of that address
cycle where an address match occurred; interrupts resulting from subsequent data transfers clear MAAS.
A data transfer can then be initiated by writing to I2CnDR for slave transmits or dummy reading from
I2CnDR in slave-receive mode. The slave negates SCLn between byte transfers. SCLn is released when
I2CnDR is accessed in the required mode.
17.5.8.1

Slave Transmitter and Received Acknowledge

In the slave transmitter routine, the received acknowledge bit (I2CnSR[RXAK]) must be tested before
sending the next byte of data. The master signals an end-of-data by not acknowledging the data transfer
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
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C module to become the I
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C devices to be reset. Thus, SDAn can be negated low by another
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C module is coming out of reset and will stay low indefinitely. The following
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C module to generate SCLn so that the device driving SDAn can
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C bus master out of reset and drive
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