Master Read; Master Write; Controller Interrupts - Freescale Semiconductor MPC8313E Family Reference Manual

Security Engine (SEC) 2.2
The SEC does not dynamically adjust its own transaction priorities. System software, however, can adjust
SEC transaction priority in realtime, with the change in priority taking effect immediately.
14.6.2.2

Master Read

Here is more detail on the sequence of events for an system bus read with the controller as master:
1. Channel asserts its bus read request to the controller.
2. Channel furnishes external read address, internal write address, and transfer length.
3. Controller sends request acknowledge to channel.
4. Controller asserts request to the system bus through the Magenta master interface.
5. Controller waits for system bus read to begin.
6. When bus read begins, controller receives data from the master interface and performs a write to
the appropriate internal address supplied by the channel. Data may be realigned byte-wise by the
controller if either:
— The read did not begin on a 32-bit word boundary, or
— The previous write to an execution unit's input FIFO did not end on a 32-bit word boundary.
7. Transfer continues until the bus read is completed and the controller has written all data to the
appropriate internal address. The master interface will continue making bus requests until the full
data length has been read.
When the SEC performs a transaction as master, it is possible for the intended slave to terminate the
transfer due to an error. SEC transaction requests are posted to the MPC8313E target queue, after which
the MPC8313E takes responsibility for completing the transaction or signaling error. An error in an
SEC-initiated transaction will also be reported by the SEC through the channel interrupt status register.
The host will be able to determine which channel generated the interrupt by checking the ISR for the
channel ERROR bit.
14.6.2.3

Master Write

Here is more detail on the sequence of events for an system bus write with the controller as master:
1. Channel asserts its bus write request to the controller.
2. Channel furnishes internal read address, external write address, and transfer length.
3. Controller sends request acknowledge to channel.
4. Controller performs a read from the appropriate internal address supplied by the channel, loads the
write data into its FIFO, asserts a request to the system bus through the Magenta master interface,
and waits for the system bus to become available.
5. When the system bus becomes available, controller writes data from its FIFO to the master
interface.
14.6.3

Controller Interrupts

All interrupt outputs from other SEC blocks are fed to the controller as interrupt conditions. In addition,
the controller itself detects some interrupt conditions. The controller maintains an interrupt status register
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
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